Abstract: According to a presently preferred embodiment of the present invention, a method for interfacing a floating point-based process with an integer-based process is described, the method having the steps of providing a floating point process, providing an integer process, initiating a transfer of data from said floating point process to said integer-based process, the transfer having the steps of selecting a memory location containing a floating point value to be handed off to the integer-based process, determining whether the memory location contains a positive number or a negative number, computing the absolute value of the value in the memory location, adding a magnitude of 0.5 to the absolute value, multiplying, if the result of the determining step was negative, the results of the adding step by -1, and converting the results of the multiplying step to integer form.

Abstract: A method is provided for performing a fast Discrete Cosine Transform (DCT) and a fast Inverse Discrete Cosine Transform (IDCT) in a software implementation. The method provided exploits symmetries found in both the DCT and IDCT. As a result of the symmetries found in the DCT and IDCT, both transforms may be performed using a combination of look-up tables and butterfly operations, thus employing only a small number of additions and subtractions and no multiplications. Furthermore, there is provided an aspect of the present invention which exploits the excess precision available in current central processing units (CPUs) relative to the precision required by the DCT and IDCT calculations.

Abstract: A method and an apparatus for controlling calculation error produced by the accumulation error due to digit truncation in a non-integer computation. The error is eliminated by controlling the values of LSB, C.sub.in and the addition/subtraction selecting signal as, so that C.sub.in is not necessarily equal to C.sub.in. Considering a even number of cascaded pipelines, C.sub.in in the odd pipelines is set as 0, wherein C.sub.in in the even pipelines is set as 1. The resultant error is thus eliminated mutually by odd and even pipelines.

Abstract: An IEEE 754 standard floating point multiply instruction for binary extended precision format can be executed with a quad word format on an S/390 process. The multiplication calculation multiplies each partition by each other. In the multiplication calculation process dataflow process of either operand is a denormalized number, they are normalized at a stage which creates an expanded exponent range of one more bit, and the calculation continues to a parallel path multiplexor stage, but if neither operand is denormalized then the exponent of the number is expended and the calculation splits into four parallel paths, wherein two operand's sign bits are processed in a sign calculation block stage, the operands' two 16 bit binary exponents are processed by an exponent conversion block stage, and a partition multiplicand significand block stage receives a 113 bit multiplicand significand input for a fourth path.

Abstract: A data interpolating filter is disclosed, in which a wave digital filter is used for processing two-channel data with one data path. A sample and hold part samples and holds data, and selectively provides the sampled and held data for at least two different channels. An adapter filters the sampled and held data from the sample and hold part to produce interpolated data. The adapter filters the sampled and held data using a selectable one of at least two different filter coefficients, and a filtering signal delaying part delays the interpolated data in response to selecting signals.

Abstract: In order to enable calculation of the square of a number comprising many digits by means of an arithmetic circuit which is arranged for the parallel processing of numbers having a substantially smaller number of digits, the number to be squared is subdivided into sub-numbers having a number of digits which is compatible with the arithmetic circuit, the individual sub-numbers being successively processed. For faster processing in the case of squaring operations, the multiplier circuit provided in the arithmetic circuit includes a position shift circuit capable of performing a shift of one position to the left in the case of multiplication of given pairs of sub-numbers, which shift corresponds to a multiplication by the factor 2. As a result, squaring can be performed while using fewer technical means. A method operating on the basis thereof so as to form the square of a large number modulo another large number is also disclosed.

Abstract: A method using replication of distributed arithmetic logic circuits and recursive interpolation of reduced angular increments of sine and cosine sum constants in logic look-up tables, permits the computation of vector rotation and large FFTs in a unitary field programmable gate array chip without required off-chip memory for storing constants.

Abstract: A random number generator based on naturally occurring events in which directional randomness of radioactivity is exploited to generate a random number sequence. Radiation emissions from a radiation source are detected at different spatial locations about the radiation source. A unique numerical value is assigned to radiation detected at the different spatial locations. A random number sequence comprising numerical values is generated depending upon which spatial location radiation is detected.

Abstract: An apparatus that includes a logarithm based processor (216) having at least one digital logarithm converter (202) and an audio amplifier (208) responsive to the logarithm based processor (216).

Abstract: A fused floating point multiply-and-accumulate unit includes a multiplier which uses a modified Booth's algorithm to generate a sum and a carry representing a product of mantissas. An artifact of this algorithm is that the sum or carry may represent a negative value even though both mantissas are positive. The negative value may have a sign bit from sign extension or sign encoding of partial products in the multiplier. An artifact of the signed bit is a false carry out that results from canceling the sign bit. A 3-input adder simultaneously combines the sum and carry from the multiplier and performs the accumulation. The adder includes carry correction logic to suppress false carries and prevents a false carry from affecting more significant bits of the value being accumulated.

Abstract: The present invention relates to a method and apparatus for performing double precision operations using a single type of instruction, wherein a shift bit in a status register is cleared responsive to an operation between signed and signed operands or between unsigned and unsigned operands and the shift bit is cleared responsive to an operation between signed and unsigned operands or unsigned and signed operands. An accumulated result is shifted to the right when the shift bit changes state in order to accomplish a shift and a multiplication to be performed simultaneously responsive to a single type of instruction.

Abstract: An arithmetic circuit with a small number of parts performs high-speed arithmetic operations for calculating a square-root of a sum of squares of two numbers. Absolute values of two inputs S.sub.in1 and S.sub.in2 are determined by absolute value calculators and are compared by an absolute value comparator According to the comparison result, a first multiplexer selects the smaller of the two absolute values and a second multiplexer selects the larger of the two absolute values. The smaller absolute value is shifted by a 2-bit right shifter and by a 3-bit right shifter respectively, and the obtained shifted results are added together by a (N-2)-bit adder. The sum of the shifted values is then added by a N-bit adder to the larger absolute value. A square-root of the square-sum of two inputs S.sub.in1 and S.sub.