Abstract: A method and system for secure cable modem initialization in a data-over-cable system is provided using a secure protocol server. The method includes sending a unique identifier, such an Internet Protocol ("IP") address and a selected time-value, such as an approximate message send time-value, in a configuration file from a protocol server such as a Trivial File Protocol server ("TFTP"). A message integrity value is calculated using the unique identifier, the selected time-value and one or more configuration parameters in a pre-determined order with a cryptographic hashing function. The message integrity value is added to the configuration file. A cable modem receives the configuration file from the TFTP server and uses the message integrity value to authenticate the configuration file and determine if the configuration file was sent within a pre-determined period of time (e.g., 5 seconds) from the TFTP server. If not, the configuration is discarded by the cable modem.

Abstract: A system for booting a multi-processor computer. If a normal boot attempt fails, different processors are selected, one-at-a-time, for performing the boot routine. During the boot routing, all other processors are held inactive. After boot, processors are tested for health. Non-healthy processors are held inactive, and healthy processors are activated as usual.

Abstract: A method of booting a portable computing device or a personal digital assistant (PDA) is described. In one embodiment, the PDA comprises a boot ROM, a RAM, and a connector for connecting to an external floppy disk drive (FDD). Operating system software and application software for the PDA is stored on a disk in FDD. To boot the PDA, the PDA is connected to the external FDD, then powered up. The PDA is hardwired to begin executing code from the boot ROM, which contains a program to transfer code from the FDD to the RAM, then jump to an entry point in the newly loaded code in the RAM. The PDA is then disconnected from the FDD. To configure the PDA with different operating system and/or different application software, the FDD is loaded with a disk storing this different software and the boot process is repeated. Thus, the PDA can be configured to support any number of different operating systems and any number of different applications despite having a limited capacity of RAM.

Abstract: A system and method for managing client authorization to access remote data repositories through a middle tier server such as a web server. Client remote data repository access is intercepted by the middle tier server and the server is searched for stored credentials permitting client access to the remote data repository. If found, the stored credentials are used to authenticate access without further interaction with the client system. If no stored credentials are found, the server requests credentials from the client and passes them to the remote data repository for validation. Validated credentials are stored by the server for future use and indexed by a client identifier. Permitted remote data repository access is stored with the validated credentials. Access to a mounted remote file system is not permitted without authorization even if the remote file system would not otherwise require authorization.

Abstract: A cache has programmable, finely ganular, locked-down regions within a way or way(s) so that the contents of the locked-down regions are not evicted. The finely granular locked-down regions need not be contiguous and are programmed as either "locked-valid" or "locked-invalid" to provide general purpose memory that is local and private to the processor or for masking defected cache lines or portions thereof. Finely granular, programmable spatial regions of the cache that are locked-down are preferably, although not exclusively, programmed through two additional states to the standard MESI (Modified, Exclusive, Shared, Invalid) protocol for multipurpose cache coherency.

Abstract: A kit in accordance with the invention is disclosed that allows for simultaneous connectivity of a variety of SCSI devices to a SCSI card via a SCSI bus. Such SCSI devices include internal narrow, internal wide, external narrow, and external wide devices. A kit in accordance with the invention includes a terminator-adapter. The terminator-adapter includes a first wide connector, a second narrow connector, and a wide bus including an upper and lower bus. The upper bus is coupled to the wide connector and is first and second connector as well as a soft terminator. By enabling the soft terminator, the terminator-adapter behaves as a wide bus terminator. By disabling the soft terminator, the terminator-adapter behaves as a wide-to-narrow adapter. A kit in accordance with the invention may further include a wide cable and a SCSI card. In various embodiments, the SCSI card includes a wide internal connector and a narrow internal connector.

Abstract: A computer system power-on security control apparatus is disclosed to provide shielding against unauthorized access to the computer systems. Firmware-level protection is provided instead of the conventional implementation at the operating system level. Repeated power-on and -off cycles inevitable in the process of trial entry of the password of the computer system can be avoided altogether, reducing the risk of potential damages to delicate subsystems in the computer while repeated trial of the password is attempted.

Abstract: A transfer of data between the first clock domain to the second clock domain is synchronized in a situation in which the first clock signal in the first clock domain is generated from a source independent from the second clock signal in the second clock domain. The ratio of one frequency to another is determined along with the phase relationship between the two clock signals during a selected period of time. Then, the phase relationship is predicted for a future period of time. This prediction of the relationship between the two clock signals serves as an input to a control mechanism, which prevents sampling of data and control signals when they are transitioned from one state to another.

Abstract: A computer system is disclosed having two structures, a mobile core unit and an enclosure capable of enclosing and cooperating with the core unit. The core unit has all of the components of a general purpose computer except for a display and source of power. This core unit by itself is non-functional as a computer unless it is in electrical contact with the enclosure. The enclosure has several connector ports for attachment of peripherals to the system.

Abstract: A system for facilitating determination of accurate timing of execution of a computer program fragment by a digital computer comprises a clock resolution determination subsystem and an iteration number determination subsystem. The clock resolution determination subsystem determines a clock resolution value representing a resolution of a clock provided by the digital computer. The iteration number determination subsystem uses the clock resolution value, and maximum and minimum desired time interval values, to determine an iteration number value, the iteration number representing a number of iterations for execution of the computer program fragment to provide accurate timing of the computer program fragment by the digital computer.

Abstract: The present invention provides a method of reducing the amount of memory required to scan a given data string for the presence of computer viruses or other data traits of interest including the steps of 1) loading into a memory of a computer a set of generic features that are functionally similar to standard computer virus signatures, but tend to be less specific to particular viruses, 2) locating occurrences of the generic features within the data string, 3) applying a first mapping from the occurrences located during step 2) to obtain a subset of standard signatures, 4) loading the subset of standard signatures into a memory of said computer, 5) locating occurrences within the data string of all signatures from the subset of standard signatures, and 6) applying a second mapping from the occurrences located during step 5) to identify a set of computer viruses that are likely to be present in the data string.

Abstract: A data processing system on an integrated circuit 42 with microprocessor 1 and peripheral devices 60-61 is provided with an emulation unit 50 which allows debugging and emulation of integrated circuit 42 when connected to an external test system 51. Microprocessor 1 has in instruction execution pipeline which has several execution phases which involve fetch/decode units 10a-c and functional execution units 12, 14, 16 and 18. The pipeline of microprocessor 1 is unprotected so that memory access latency to data memory 22 and register file 20 can be utilized by system program code which is stored in instruction memory 23. Emulation unit 50 provides means for emulating the unprotected pipeline of microprocessor 1 and for rapidly uploading and downloading memories 22-23. Emulation unit 50 operates in a manner to prevent extraneous operations from occurring which could otherwise affect memories 22-23 or peripheral devices 60-61 during emulation.

Abstract: A DVD assembly, and an associated method, for a convergent device, such as a television converged into a computer. The DVD assembly is integrated into the convergent device to facilitate ease of user control over operation of the DVD assembly. Common control interfaces which include the "look and feel" of the control interfaces otherwise used by the convergent device simplify operational control over operation of the DVD assembly.

Abstract: A foldable display screen notebook computer with touch screen operational capabilities which folds outward to form a viewing angle for the display screen which can be varied as a function of the axis of pivot of the display screen and where the display section and its component back section are detachable from the base section providing a modular concept which facilitates multiple computer function capability while minimizing cost expenditure and size for features which are not needed or which are not desirable during the operation under consideration. The modularity options provide for a notebook computer of minimal physical size and affordability. The display screen can be oriented to provide a space saving foot print and includes optional electronics and programming to provide, amongst other features, a portrait view of the screen.

Abstract: An interpolation circuit for a digital filter which is small in circuit scale, operates at a high speed and is low in power consumption. The digital interpolation filter circuit includes front-end circuit 1 which outputs added value .SIGMA..sub.i of input data and the last data, and filter unit 2. Filter unit 2 includes delay circuit unit 3 which delays added value .SIGMA..sub.i of one clock and two clocks intervals, and outputs the delayed values, bit shift circuit unit 4 which inverts the signs of the added value and data obtained by delaying the added value 2 clocks interval and outputs resulting values and which shifts the data delayed one clock interval from the added value, 3 bits and one bit making multiplication of the delayed added value by 8 and 2, respectively, and outputs resulting values, adder 5 for adding the outputs of bit shift circuit unit 4 for each data having the same delay amount, and bit shift circuit 6 for shifting a result of the addition by 4 bits to divide the addition result by 16.

Abstract: This invention provides a core computer unit that contains all of the components of a conventional computer however will not function unless it is positioned in an enclosure. The enclosure dictates the computer function, the core unit supplies the computer components. The core unit remains dormant and non-functional until it is positioned in a compatible enclosure.

Abstract: A method for transferring data from a first clock domain to a second clock domain. A first clock signal is generated for the first clock domain from a base clock signal. A second clock signal is generated for the second clock domain from the base clock signal. A phase relationship is detected between the first clock signal and the second clock signal. Data is transferred from the first clock domain to the second clock domain using the phase relationship between the first clock signal and the second clock signal.

Abstract: Disclosed is a personal computer system which includes a central processing unit (CPU) coupled to a direct access storage device (DASD) and a random access memory (RAM). A flash memory module is coupled to the CPU and an input/output (IO) bus and includes a basic input output system (BIOS) stored therein. The BIOS is effective for responding to the energization of the computer system by initiating a power on self test (POST). The BIOS is further operative on completion of the POST for transferring a portion of BIOS from the module to the RAM and for transferring control of the of the computer system to the BIOS portion. The portion of BIOS is operative to load a protected mode operating system (OS) into RAM and transfer control to the OS. The system further includes a logic circuit coupled to the flash memory module and the IO bus for allowing the BIOS in flash memory to be accessed while the protected mode OS is running.

Abstract: The present invention relates to a recovery function from a system failure such as a power failure and a media failure such as a breakage of disk at a transaction processing system of a plurality of user environment, and is applied in carrying out a checkpoint to reduce an amount of work required for failure recovery, and particularly to a fuzzy checkpoint method which is a method of enhancing a system performance by not interrupting other transactions ever for a moment at the time of checkpoint. According to the present invention, the occurrance of dangling transaction is prevented by deleting the corresponding transaction entry from the transaction table during performing of the redo step, for the transactions terminated between the point of time when the checkpoint start log record of the last completed checkpoint is logged and the point of time when the checkpoint end log record is logged.

Abstract: A method and a circuit arrangement for implementing timing between a microprocessor and its peripheral devices. An address bus and a data bus connect the microprocessor to the peripheral devices to transfer data from the microprocessor to a selected peripheral device, corresponding to writing to the peripheral device, and from a selected peripheral device to the microprocessor, corresponding to reading from the peripheral device. The method comprises generating to the peripheral devices (a) a signal controlling reading (Output Enable), which enables a peripheral device to apply data to the data bus, and (b) a signal controlling writing (Write Enable), which enables data to be written from the data bus to a peripheral device.