Abstract: The present invention relates to an apparatus and method for improving the probability of a successful, subsequent attempt to boot a computer system after a failed system boot. The method comprises the steps of: (a) identifying a cause of the failed system boot; and (b) modifying parameters related to an identified cause of a failed system boot and/or taking evasive action based on an identified cause of a failed system boot.

Abstract: A self-timed link between two elements in a computer system is initialized. Each element sends an initialization request to the other. If successfully received, the elements exchange signals with oscillation-free segments over multiple clock cycles. If successful, the elements indicate to each other that initialization is complete. Optionally, a link operation parameter can be sent with the initialization complete indication for post-initialization link control.

Abstract: An external interrupt port is installed for writing a password into a random access memory by monitoring low voltage with an interrupt when a battery is turned off and on instantaneously and performing ignition off processing. During Random access memory initialization the system disables an external interrupt and initializes output of ports containing the external interrupt port when an ignition switch is turned on, next makes a password check just after initializing output of the ports, then enables an external interrupt and executes initialization.

Abstract: A VRAM-based parity engine for use in a disk array controller is disclosed, in which the parity arithmetic operation is carried out in a fast and effective manner, thereby improving the performance of the RAID system. Particularly, the parity data arithmetic operation is not resorted to a processor, but to a VRAM, thereby realizing a high speed operation. In the disk array controller, a VRAM (video RAM) is used, in such a manner that the reading, updating and writing are made to be overlapped during the arithmetic operation, thereby promoting the speed of the arithmetic. Therefore, a relatively large capacity memory can be formed compared with the conventional SRAM, and therefore, a temporary buffer memory within the parity engine is used as a parity cache, thereby doubling the performance.

Abstract: A data processor has a ROM that holds a boot program for causing the CPU to transfer a debug program from a serial interface circuit to a debug-use RAM area. When supplied externally with an SDI boot command, the serial interface circuit outputs an SDI interrupt request signal (SDI.sub.-- boot) to an interrupt controller. The signal causes the CPU to execute the boot program. Debug operations are varied as per the contents of the downloaded debug program, and data exchanges upon debugging are carried out serially.

Abstract: A storage device for use with a computer is provided, the device includes self diagnostics and configuration. The device is adapted to recognize when the host computer system requests an operating system from the device, and instead of providing the operating system, provides its own diagnostic and configuration software. When the software executes on the computer, the software causes a user interface to be generated, which provides various configuration and diagnostic options to a user. Upon termination of the self diagnostic and configuration software, the device provides the operating system to the computer such that the start up sequence is resumed.

Abstract: A binary adder circuit includes carry evaluation circuits that encode a carry production control signal using two signal values (V, W) such that V=W=0 indicates a carry kill, V=W=1 indicates a carry generate and V.noteq.W indicates a carry propagate. The carry evaluation circuit may be implemented in static or dynamic CMOS logic.

Abstract: The program system of a complex computer system is highly customer-specific, for which reason the start-up varies considerably. The start-up system of such a computer system must therefore be very flexible. On the other hand, however, early and close monitoring of the complex start-up should be ensured. These requirements are satisfied by a start-up system which has a start-up table generated off-line.

Abstract: New objects in an object-oriented environment are configured and initialized for a specific container location using a configurator object. Each container in the system will have a configurator object associated with the container. The configurator object for each container will contain the configuration attributes for their respective container. The configurator object will use the container attributes for the container where the newly created object is to be stored and will apply that container's attributes to the newly created object.

Abstract: A method and device of plugging and immediately playing a CPU. The user sets the settings of working frequency and voltage of the CPU through the system firmware of a computer. Then, the system stores the settings in a storage device, and the CPU is reset by a reset unit, thereby the multiple frequency controller and voltage converter take control of the operation to instruct the CPU to determine the working speed by a new multiple frequency ratio and to change the voltage into a working voltage corresponding to the model and brand of the CPU without the use of jumpers or switches. The goal of plugging and immediately playing of a CPU is achieved.

Abstract: A method, apparatus and computer program product are provided for verifying integrity of predefined data structures in a computer system. A central software failure map is stored which includes for each of the predefined data structures a corresponding in-flux bit. The corresponding in-flux bit is set in response to a request to update one of the predefined data structures. Then updating of one of the predefined data structures is performed. The corresponding in-flux bit is reset in response to completing the update of the one of the predefined data structures. During recovery, the corresponding in-flux bits are checked to identify any unstable data structures.

Abstract: This structure is a stand alone or laptop computer that has a detachable hands-free mobile computer housed therein. The stand alone (or laptop) computer and the detachable hands-free mobile computer each can operate independent of or together with the other computer. Also each computer can communicate with the other during operation while connected or disconnected from each other.

Abstract: A distributed method and system for excluding segments from use in bypassing a failed component. Prior to failure of a segment, the restoration system at a central location identifies each path in the communications network. A path is a unique sequence of installations that a segment traverses. The restoration system then creates a mapping of the ports of the restoration nodes to the paths of the segments connected to each port. The restoration system then identifies for each path the set of paths that are interdependent. A pair of paths are interdependent when both paths traverse a common pair of installations. The restoration system then downloads to each restoration node the mappings for its ports along with an indication of the paths that are interdependent with the path of each segment connected to the restoration node.

Abstract: A converter, which may be used for implementing either logarithmic or inverse-logarithmic functions, includes a memory, a multiplier, and an adder. The memory stores a plurality of parameters which are derived using a least squares method to estimate a logarithmic or inverse-logarithmic function over a domain of input values.

Abstract: The ringing detector of the invention receives data representing pixel values of a plurality of pixels including: a remarked pixel; a number L (where L is a natural number) of neighboring pixels which are located in the vicinity of the remarked pixel; and a number M (where M is a natural number) of surrounding pixels which are more distant from the remarked pixel than the neighboring pixels are, thereby generating a ringing constant t indicating whether or not a ringing exists in the vicinity of the remarked pixel. The ringing detector includes: a pixel value variation detector for calculating a value x corresponding to a variation in the pixel values of the neighboring pixels; a distance detector for calculating a value y corresponding to a distance between the pixel values of the surrounding pixels and a barycenter of the pixel values of the remarked pixel and the neighboring pixels; and a ringing constant calculator for calculating the ringing constant t based on the values x and y.

Abstract: Launch time for a computer program is reduced by logging hard disk accesses during an initial launch, then processing the log file to accelerate subsequent launches. The log file is processed by identifying all the file portions accessed during the launch, eliminating any duplicate cluster accesses, then sorting the remaining accesses. The disk access log entries are sorted by physical address or are grouped by file, then organized by logical address within each group. The processed log file is stored with the application program. When the application program is launched thereafter, the processed log file is accessed first. All the disk accesses in the log file are performed moving all the data into RAM cache. When the program launch resumes, the launch occurs faster because all the data is already in cache.

Abstract: A floating-point arithmetic processing apparatus has a circuit for generating a limit value for normalization shift by subtracting an exponent of the minimum value of a normalized number from a value of an exponent of an intermediate result, and a circuit for generating, as a normalization shift number, smaller one of a shift number necessary for making the mantissa of the intermediate result a normalized number and the limit value for normalization shift. The floating-point arithmetic processing apparatus further has a circuit having a circuit for detecting a condition for overflow before the rounding process and a circuit for generating a value in the case of overflow, so that a predetermined value is delivered as a final result only when the overflow condition is detected before the rounding process but in the other case, a result obtained by performing the normalization process and the rounding process is delivered.

Abstract: A floating point addition and subtraction circuit includes a comparison subtraction circuit receiving two operands to be processed for making a comparison in the size between their exponent parts so as to subtract the smaller exponent part from the larger one, the comparison subtraction circuit providing the comparison result and the subtraction result. A mantissa selecting circuit and a shift circuit align the mantissa of the operand. Leading zero counting circuit counts the number of zeros successively positioned in the high order direction from the least significant bit of the mantissa of the operand having the smaller operand. Comparator circuit compares the counting result and the subtraction result by the comparison subtraction circuit, to thereby detect a sticky bit according to the comparison result.

Abstract: A method in which unauthorized persons can be excluded from accessing an HTTP-compliant, server-based application through a client processor when the session is suspended. The method requires that authenticated access is initially bound to the application and client reauthentication by the application is required in order to resume. For persistent unauthorized users, the client processor is bound to a substituted logical partition at the server that emulates a session, notifies security, and logs the activity as evidence.

Abstract: The invention relates to a multiplier for the multiplication of at least two figures in an original format. Each of said figures is fed to a first converter for conversion of each of said figures in the product of a first binary number representing a power of 2, and a second binary number representing a signed power of 3, the exponents of the powers of 2 of the concerning figures being fed to a first adder and the exponents of the powers of 3 of the concerning figures being fed to a second adder, whereby the combined respective outputs of the first adder and the second adder represent the multiplied value of said figures, and the resulting powers of 2 and 3 as available at the outputs of the first and second adder being fed to a second converter for conversion of the multiplied value into the original format.