Abstract: A semiconductor module includes: semiconductor devices; a resin mold that integrally seals the semiconductor devices; and external terminals that are disposed at a lateral side of the resin mold along a direction perpendicular to a thickness direction of the semiconductor devices. Each semiconductor device includes an insulated gate semiconductor device having a gate electrode, a first electrode, and a second electrode. In the insulated gate semiconductor device, carriers move from the first electrode to the second electrode through a channel provided by a voltage applied to the gate electrode. The external terminals include: a gate terminal electrically connected to the gate electrode; a first terminal electrically connected to the first electrode; and a second terminal electrically connected to the second electrode. The gate terminal and the second terminal, which are electrically connected to an identical semiconductor device, are not adjacent to each other.

Abstract: The present disclosure provides a semiconductor chip including a functional area, a first end, a second end, a third end, and a connecting portion. The functional area has first and second sides opposite to each other. The first end is disposed on the first side and the third end is disposed on the first side, wherein the semiconductor chip is switched on or off according to the drive signal received between the third end and the first end, and the connecting portion is disposed on the first side of the functional area and connected to the first end and the third end, wherein when the temperature rises above the a first temperature, the connecting portion is in a conductive state, and when the temperature drops to be not higher than a third temperature, the connecting portion is in an insulated state.

Abstract: A semiconductor device is provided. In an embodiment, the semiconductor device comprises a control region, a first power region, a second power region, an isolation region and/or a short circuit structure. The control region comprises a control terminal. The first power region comprises a first power terminal. The second power region comprises a second power terminal. The isolation region is between the control region and the first power region. The short circuit structure extends from the first power region, through the isolation region, to the control region. The short circuit structure is configured to form a low-resistive connection between the control region and the first power region during a failure state of the semiconductor device.

Abstract: Some embodiments include an apparatus having horizontally-spaced bottom electrodes supported by a supporting structure. Leaker device material is directly against the bottom electrodes. Insulative material is over the bottom electrodes, and upper electrodes are over the insulative material. Plate material extends across the upper electrodes and couples the upper electrodes to one another. The plate material is directly against the leaker device material. The leaker device material electrically couples the bottom electrodes to the plate material, and may be configured to discharge at least a portion of excess charge from the bottom electrodes to the plate material. Some embodiments include methods of forming apparatuses which include capacitors having bottom electrodes and top electrodes, with the top electrodes being electrically coupled to one another through a conductive plate. Leaker devices are formed to electrically couple the bottom electrodes to the conductive plate.

Abstract: What is provided is a pattern forming method for forming a pattern on a surface to be processed of an object, the method including: a first layer forming step of forming a first layer containing a compound having a protective group that is decomposable by an acid and also decomposable by light, on the surface to be processed; a second layer forming step of forming a second layer containing a photoacid generator that is configured to generate an acid by exposure, on the first layer; an exposure step of exposing the first layer and the second layer to form a latent image including an exposed region and an unexposed region, on the first layer; and a disposition step of disposing a pattern forming material in the exposed region or the unexposed region.

Abstract: Microelectronic assemblies, and related devices and methods, are disclosed herein. For example, in some embodiments, a microelectronic assembly may a die having a front side and a back side, the die comprising a first material and conductive contacts at the front side; and a thermal layer attached to the back side of the die, the thermal layer comprising a second material and a conductive pathway, wherein the conductive pathway extends from a front side of the thermal layer to a back side of the thermal layer.

Abstract: A semiconductor device includes a stacked structure, channel layers passing through the stacked structure, a well plate located under the stacked structure, a source layer located between the stacked structure and the well plate, a connection structure coupling the channel layers to each other and including a first contact contacting the source layer and a second contact contacting the well plate, and an isolation pattern insulating the source layer and the well plate from each other.

Abstract: Provided are an OLED, display panel and display device. The OLED includes a first electrode, a second electrode, a light emitting layer and at least one blocking layer. The second electrode is arranged opposite to the first electrode. The light emitting layer is arranged between the first electrode and the second electrode. The blocking layer is arranged between the light emitting layer and the second electrode and/or between the light emitting layer and the first electrode. Each blocking layer of the at least one blocking layer comprises at least two blocking materials, electron mobility of at least one blocking material of the at least two blocking materials is lower than a first preset value, electron mobility of at least another blocking material of the at least two blocking materials is higher than a second preset value, and the first preset value is lower than the second preset value.

Abstract: An organic light emitting diode display device includes a substrate, an active layer disposed on the substrate and including a metal oxide-based semiconductor, a gate electrode disposed on the active layer, an insulating layer disposed on the gate electrode, source and drain electrodes disposed on the insulating layer, a light emitting element on the source and drain electrodes, and a gate insulating layer between the active layer and the gate electrode. The gate insulating layer includes first and second gate insulating layers. The first gate insulating layer directly contacts the active layer and has a first amount of nitrogen. The second gate insulating layer is disposed on the first gate insulating layer and has a second amount of nitrogen that is different from the first amount of nitrogen.

Abstract: A semiconductor structure and a fabrication method of the semiconductor structure are provided in the present disclosure. The semiconductor structure includes a substrate, where the substrate includes a shielding region having a first area; a first shielding layer on the substrate, where a first shielding structure is in the first shielding layer of the shielding region, and the first shielding structure has a first density; a second shielding layer on the first shielding layer, where a second shielding structure is in the second shielding layer of the shielding region, and the second shielding structure has a second density which is less than the first density; and an electrical interconnection structure, electrically interconnecting the first shielding structure with the second shielding structure and enabling the first shielding structure grounded.

Abstract: A method of manufacturing a semiconductor device includes forming a via including a first conductive material on an inner wall of a trench on a substrate. The method further includes forming a first insulating interlayer on the substrate. The first insulating interlayer covers the via and partially fills the trench, and the first insulating interlayer has a non-flat upper surface. The method further includes forming a polishing stop layer on the first insulating interlayer, forming a second insulating interlayer on the polishing stop layer, in which the second insulating interlayer fills a remaining portion of the trench, planarizing the second insulating interlayer until the polishing stop layer is exposed, and etching the polishing stop layer and the first and second insulating interlayers using a dry etching process until remaining portions of the polishing stop layer except for a portion of the polishing stop layer in the trench are removed.

Abstract: The present application relates to the technical field of semiconductor manufacturing, in particular to a device integrated with a three-dimensional MIM capacitor and a method for manufacturing the same. The device comprising: a first dielectric layer, a first conductive metal structure being formed in the first dielectric layer; and a second dielectric layer, plurality of MIM capacitors being formed in the second dielectric layer, the bottom of each of the MIM capacitors being connected to the first conductive metal structure, and the plurality of three-dimensional MIM capacitors being arranged as array in a two-dimensional plane presented by the second dielectric layer; wherein each of the three-dimensional MIM capacitors sequentially comprises an upper electrode, a dielectric layer covering the bottom sides of the upper electrode, and a lower electrode layer covering an outer surface of the dielectric layer; the lower electrode layer is connected to the first conductive metal structure.

Abstract: A semiconductor structure includes a first layer, a second layer, a first interconnection layer, and a second interconnection layer. The first layer includes an upper electrode pattern, and the second layer includes a lower electrode pattern, wherein the upper electrode pattern is opposite to the lower electrode pattern. The first interconnection layer includes a plurality of first interconnect structures electrically connected on the upper electrode pattern. The second interconnection layer includes a plurality of second interconnect structures electrically connected on the lower electrode pattern. The first interconnect structures on the upper electrode pattern are hybrid bonded with the second interconnect structures on the lower electrode pattern. Therefore, the upper electrode patterns and the lower electrode patterns are joined by hybrid bonding to form a capacitor element.

Abstract: The present invention provides an improved hole transport material, manufacturing method and an electroluminescent device having a central core made of tetramethyldihydrophenazine. A structural formula of the hole transport material is: The present invention adjusts the structure of donor units to change a capability of providing electrons thereof, designs a hole transport material of a high mobility and reasonable wires, and the material improves the compounding efficiency.

Abstract: The present disclosure relates to a radio frequency (RF) device including a device substrate, a thinned device die with a device region over the device substrate, a first mold compound, and a second mold compound. The device region includes an isolation portion, a back-end-of-line (BEOL) portion, and a front-end-of-line (FEOL) portion with a contact layer and an active section. The contact layer resides over the BEOL portion, the active section resides over the contact layer, and the isolation portion resides over the contact layer to encapsulate the active section. The first mold compound resides over the device substrate, surrounds the thinned device die, and extends vertically beyond the thinned device die to define an opening over the thinned device die and within the first mold compound. The second mold compound fills the opening and directly connects the isolation portion of the thinned device die.

Abstract: Embodiments of the disclosure provide a capacitor for an integrated circuit (IC). The capacitor may include a first vertical electrode on an upper surface of a first conductor within a first wiring layer. A capacitor dielectric may be on an upper surface of the first vertical electrode. A second vertical electrode may be on an upper surface of the capacitor dielectric. The second vertical electrode is vertically between the capacitor dielectric and a second conductor. An inter-level dielectric (ILD) layer is adjacent to each of the first vertical electrode, the capacitor dielectric, and the second vertical electrode. The ILD layer is vertically between the first conductor and the second conductor.

Abstract: Some embodiments include an assembly having channel material structures extending upwardly from a conductive structure. Anchor structures are laterally offset from the channel material structures and penetrate into the conductive structure to a depth sufficient to provide mechanical stability to at least a portion of the assembly. The conductive structure may include a first conductive material over a second conductive material, and may be a source line of a three-dimensional NAND configuration. Some embodiments include methods of forming assemblies to have channel material structures and anchor structures.

Abstract: A method includes forming a first conductive feature on a substrate, forming a via that contacts the first conductive feature, the via comprising a conductive material, performing a Chemical Mechanical Polishing (CMP) process to a top surface of the via, depositing an Interlayer Dielectric (ILD) layer on the via, forming a trench within the ILD layer to expose the via, and filling the trench with a second conductive feature that contacts the via, the second conductive feature comprising a same material as the conductive material.

Abstract: According to one embodiment, a semiconductor device includes at least a package substrate, an external electrode, a mounting substrate, and a mounting electrode. A signal connection point of the external electrode is provided at an end portion in a longitudinal direction of the external electrode. A signal connection point of the mounting electrode is provided at an end portion of the mounting electrode. The end portion of the mounting electrode is opposite to the signal connection point of the external electrode facing to the mounting electrode in the longitudinal direction.

Abstract: The present disclosure relates to a light emitting diode that includes a charge control layer disposed between a charge transfer layer and one electrode and including polysiloxane-based material chemically bonded to a surface of the charge transfer layer and a light emitting device having the same. The charge control layer is configured to remove a surface defect of the charge transfer layer, to transport charges stably, and to reflect a part of light passing through the charge transfer layer, and thereby enhancing out-coupling efficiency. In addition, the charge control layer regulates a charge flow from the electrode to the charge transfer layer, so that charges may be injected into an emitting material layer in a balanced manner.