Abstract: A microelectronic device comprises: a first electrode; a second electrode located vertically below said first electrode and separated by a dielectric material; and a connection wire electrically connected to said second electrode; wherein said first electrode comprises a notch located vertically above said connection wire.

Abstract: An integrated circuit package structure is provided that includes a chip carrier substrate, at least one processor die provided on the chip carrier substrate, a plurality of lateral escape wiring lines connected to and extending away from the at least one processor die, and a plurality of chips at least partially surrounding the processor die, at least one of the chips overlapping with at least one of the lateral escape wiring lines in a plan view. An interconnect structure of the chips includes at least one vertical power feed structure that is configured and positioned not to intersect with the lateral escape wiring lines in the plan view.

Abstract: Methods and apparatus for providing an assembly including a base substrate, a lid substrate, and a ring frame between the base substrate and the lid substrate to define a protected volume, where the ring frame includes through vias. A die may be contained in the protected volume. Sensor circuitry can include conductive pillars in the protected volume and the die can include circuity to determine an impedance of the pad and the pillars for tamper detection. An edge cap can be coupled to at least one side of the assembly for tamper detection.

Abstract: Disclosed is a semiconductor package comprising a logic die mounted on an interposer substrate, and a memory stack structure disposed side-by-side with the logic die. The memory stack structure includes a buffer die mounted on the interposer substrate, and a plurality of memory dies stacked on the buffer die. The buffer die has a first surface that faces the interposer substrate and a second surface that faces the plurality of memory dies. The number of data terminals on the second surface is greater the number of connection terminals on the first surface.

Abstract: An IC includes a substrate including circuitry configured to provide a receiver or a transmitter circuit. A metal stack is over the semiconductor surface including a top metal layer and a plurality of lower metal layers. An isolation capacitor includes the top metal layer as a top plate that is electrically connected to a first node; and a top dielectric layer on the top plate with a top plate dielectric aperture. One of the plurality of lower metal layers provides a bottom plate that includes a plurality of spaced apart segments. A capacitor dielectric layer is between the top and bottom plate. The segments include a first segment electrically connected to a second node and at least a second segment electrically connected to a third node, with separation regions located between adjacent spaced apart segments. The top plate covers at least a portion of each of the separation regions.

Abstract: A perpendicular magnetic tunnel junction is disclosed wherein a metal insertion (MIS) layer is formed within a free layer (FL), a partially oxidized Hk enhancing layer is on the FL, and a nitride capping layer having a buffer layer/nitride layer (NL) is on the Hk enhancing layer to provide an improved coercivity (Hc)/switching current (Jc) ratio for spintronic applications. Magnetoresistive ratio is maintained above 100%, resistance×area (RA) product is below 5 ohm/?m2, and thermal stability to 400° C. is realized. The FL comprises two or more sub-layers, and the MIS layer may be formed within at least one sub-layer or between sub-layers. The buffer layer is used to prevent oxygen diffusion to the NL, and nitrogen diffusion from the NL to the FL. FL thickness is from 11 Angstroms to 25 Angstroms while MIS layer thickness is preferably from 0.5 Angstroms to 4 Angstroms.

Abstract: Embodiments of the present invention are directed to methods and resulting structures for integrated circuits having metal-insulator-metal (MIM) capacitors that serve as both decoupling capacitors and crack stops. In a non-limiting embodiment, an interconnect is formed on a first portion of a substrate in an interior region of the integrated circuit. A second portion of the substrate is exposed in an edge region of the integrated circuit. A MIM capacitor is formed over the second portion of the substrate in the edge region. The MIM capacitor includes two or more plates and one or more dielectric layers. Each dielectric layer is positioned between an adjacent pair of the two or more plates and a portion of the two or more plates extends over the interconnect in the interior region. A plate of the two or more plates is electrically coupled to a last metal wiring level of the interconnect.

Abstract: An apparatus is provided which comprises: a plurality of plated through holes; a material with magnetic properties adjacent to the plurality of plated through holes; and one or more conductors orthogonal to a length of the plurality of plated through holes, the one or more conductors to couple one plated through hole of the plurality with another plated through hole of the plurality such that an inductor is formed.

Abstract: Some embodiments include an apparatus having horizontally-spaced bottom electrodes supported by a supporting structure. Leaker device material is directly against the bottom electrodes. Insulative material is over the bottom electrodes, and upper electrodes are over the insulative material. Plate material extends across the upper electrodes and couples the upper electrodes to one another. The plate material is directly against the leaker device material. The leaker device material electrically couples the bottom electrodes to the plate material, and may be configured to discharge at least a portion of excess charge from the bottom electrodes to the plate material. Some embodiments include methods of forming apparatuses which include capacitors having bottom electrodes and top electrodes, with the top electrodes being electrically coupled to one another through a conductive plate. Leaker devices are formed to electrically couple the bottom electrodes to the conductive plate.

Abstract: A semiconductor device includes a first fin, a second fin, a first gate electrode having a first portion that at least partially wraps around an upper portion of the first fin and a second portion that at least partially wraps around an upper portion of the second fin, a second gate electrode having a portion that at least partially wraps around the upper portion of the first fin, and a gate-cut feature having a first portion in the first gate electrode between the first and second portions of the first gate electrode. The gate-cut feature is at least partially filled with one or more dielectric materials. In a direction of a longitudinal axis of the first fin, the gate-cut feature has a second portion extending to a sidewall of the second gate electrode.

Abstract: Embodiments include semiconductor packages and a method to form such packages. A semiconductor package includes first, second, and third microelectronic devices on a package substrate. The first microelectronic device has a top surface substantially coplanar to a top surface of the second microelectronic device. The third microelectronic device has a top surface above the top surfaces of the first and second microelectronic devices. The semiconductor package includes a first conductive layer on the first and second microelectronic devices, and a second conductive layer on the third microelectronic device. The second conductive layer has a thickness less than a thickness of the first conductive layer, and a top surface substantially coplanar to a top surface of the first conductive layer. The semiconductor includes thermal interface materials on the first and second conductive layers. The first and second conductive layers are comprised of copper, silver, boron nitride, or graphene.

Abstract: Structures are provided that include a metal-insulator-metal capacitor (MIMCAP) present in the back-end-of-the-line (BEOL). The MIMCAP includes at least one of the bottom electrode and the top electrode having a via portion and a base portion that is formed utilizing a subtractive via etch process. Less via over etching occurs resulting in improved critical dimension control of the bottom and/or top electrodes that are formed by the subtractive via etch process. No bottom liner is present in the MIMCAP thus improving the resistance/capacitance of the device. Also, and in some embodiments, a reduced foot-print area is possible to bring the via portion of the bottom electrode closer to the top electrode.

Abstract: A memory device includes a bottom electrode, an insulating layer, and a top electrode. The bottom electrode includes a plurality of carbon nanotubes. The insulating layer is disposed over the plurality of carbon nanotubes. The top electrode includes a graphene layer separated from the plurality of carbon nanotubes by the insulating layer.

Abstract: A semiconductor module is provided that includes a low side switch, a high side switch and a control chip. The low side switch and the high side switch are arranged laterally adjacent one another and coupled by a switch node connector to form a half bridge circuit. The switch node connector includes two or more branches that have an arrangement with respect to the low side switch and to the high side switch and that each have a cross-sectional area. The arrangement and the cross-sectional area of the two or more branches are selected so as to homogenise the current density distribution within the switch node connector.

Abstract: The present disclosure relates to a radio frequency (RF) device including a device substrate, a thinned device die with a device region over the device substrate, a first mold compound, and a second mold compound. The device region includes an isolation portion, a back-end-of-line (BEOL) portion, and a front-end-of-line (FEOL) portion with a contact layer and an active section. The contact layer resides over the BEOL portion, the active section resides over the contact layer, and the isolation portion resides over the contact layer to encapsulate the active section. The first mold compound resides over the device substrate, surrounds the thinned device die, and extends vertically beyond the thinned device die to define an opening over the thinned device die and within the first mold compound. The second mold compound fills the opening and directly connects the isolation portion of the thinned device die.

Abstract: A semiconductor device includes a compound semiconductor layer disposed on a substrate, a protection layer disposed on the compound semiconductor layer, and a source electrode, a drain electrode and a gate electrode penetrating the protection layer and on the compound semiconductor layer, wherein the gate electrode is disposed between the source electrode and the drain electrode. The semiconductor device also includes a plurality of field plates disposed over the protection layer and between the gate electrode and the drain electrode, wherein the plurality of field plates are separated from each other.

Abstract: Disclosed embodiments include die-edge level passive devices for integrated-circuit device packages that provide a low-loss path to active and passive devices, by minimizing inductive loops.

Abstract: Disclosed is an electroluminescent display device including a first pixel including a first sub pixel configured to emit first colored light, a second sub pixel configured to emit second colored light, and a third sub pixel configured to emit third colored light, a first electrode in the first sub pixel, an emission layer on the first electrode, a second electrode on the emission layer, and a first charge blocking layer provided below the second electrode and configured to prevent a light emission in the emission layer, wherein the first electrode is electrically connected with a driving thin film transistor in a first contact area provided in the first sub pixel, and the first charge blocking layer is overlapped with the first contact area.

Abstract: A semiconductor package system includes a substrate, a first and a second semiconductor package, a first thermal conductive layer, a first passive device, and a heat radiation structure. The first and second semiconductor package and first passive device may be mounted on a top surface of the substrate. The first semiconductor package may include a first semiconductor chip that includes a plurality of logic circuits. The first thermal conductive layer may be on the first semiconductor package. The heat radiation structure may be on the first thermal conductive layer, the second semiconductor package, and the first passive device. The heat radiation structure may include a first bottom surface physically contacting the first thermal conductive layer, and a second bottom surface at a higher level than that of the first bottom surface. The second bottom surface may be on the second semiconductor package and/or the first passive device.

Abstract: An integrated device package sized and shaped to fit in a small space, such as within a body lumen or cavity of a human patient, is disclosed. The integrated device package includes a package substrate and integrated device dies. The first and second integrated device dies are angled relative to one another about the longitudinal axis by a fixed non-parallel angle.