Abstract: Methods, techniques, and structures relating to die packaging. In one exemplary implementation, a die package interconnect structure includes a semiconductor substrate and a first conducting layer in contact with the semiconductor substrate. The first conducting layer may include a base layer metal. The base layer metal may include Cu. The exemplary implementation may also include a diffusion barrier in contact with the first conducting layer and a wetting layer on top of the diffusion barrier. A bump layer may reside on top of the wetting layer, in which the bump layer may include Sn, and Sn may be electroplated. The diffusion barrier may be electroless and may be adapted to prevent Cu and Sn from diffusing through the diffusion barrier. Furthermore, the diffusion barrier may be further adapted to suppress a whisker-type formation in the bump layer.

Abstract: Provided is a high quality III nitride semiconductor device in which, not only X-shaped cracks extending from the vicinity of the corners of semiconductor structures to the center portion thereof, but also crack spots at the center portion can be prevented from being formed and can provide a method of efficiently manufacturing the III nitride semiconductor device. The III nitride semiconductor device of the present invention includes a support and two semiconductor structures having a nearly quadrangular transverse cross-sectional shape that are provided on the support. The two semiconductor structures are situated such that one side surface of one of the two semiconductor structures is placed to face one side surface of the other of them. The support covers the other three side surfaces and of the four sides of the semiconductor structures.

Abstract: An edge termination structure for a silicon carbide semiconductor device includes a plurality of spaced apart concentric floating guard rings in a silicon carbide layer that at least partially surround a silicon carbide-based junction, an insulating layer on the floating guard rings, and a silicon carbide surface charge compensation region between the floating guard rings and adjacent the surface of the silicon carbide layer. A silicon nitride layer is on the silicon carbide layer, and an organic protective layer is on the silicon nitride layer. An oxide layer may be between the silicon nitride layer and the surface of the silicon carbide layer. Methods of forming edge termination structures are also disclosed.

Abstract: A solid-state imaging device and method of making a solid-state imaging device are described herein. By way of example, the solid-state imaging device includes a first wiring layer formed on a sensor substrate and a second wiring layer formed on a circuit substrate. The sensor substrate is coupled to the circuit substrate, the first wiring layer and the second wiring layer being positioned between the sensor substrate and the circuit substrate. A first electrode is formed on a surface of the first wiring layer, and a second electrode is formed on a surface of the second wiring layer. The first electrode is in electrical contact with the second electrode.

Abstract: A semiconductor device includes a substrate comprising an isolation region surrounding a P-active region and an N-active region. The semiconductor device also includes an N-metal gate electrode comprising a first metal composition over the N-active region. The semiconductor device further includes a P-metal gate electrode. The P-metal gate electrode includes a bulk portion over the P-active region and an endcap portion over the isolation region. The endcap portion includes the first metal composition. The bulk portion includes a second metal composition different from the first metal composition.

Abstract: Techniques for enhancing the absorption of photons in semiconductors with the use of microstructures arc described. The microstructures, such as pillars and/or holes, effectively increase the effective absorption length resulting in a greater absorption of the photons. Using microstructures for absorption enhancement for silicon photodiodes and silicon avalanche photodiodes can result in bandwidths in excess of 10 Gb/s at photons with wavelengths of 850 nm, and with quantum efficiencies of approximately 90% or more.

Abstract: At least one embodiment is directed to a semiconductor edge termination structure, where the edge termination structure comprises several doped layers and a buffer layer.

Abstract: Embodiments relate to magnetic field current sensors.

Abstract: A P-type well region in which an inverter making up an SRAM cell is formed is subdivided into two portions, which are disposed on the opposite sides of an N-type well region NW1 and are formed so that a diffusion layer forming a transistor has no curvature while causing the layout direction to run in a direction parallel to well boundary lines and bit lines. At intermediate locations of an array, regions for use in supplying power to the substrate are formed in parallel to word lines in such a manner that one region is provided per group of thirty two memory cell rows or sixty four cell rows.

Abstract: Fin-defining mask structures are formed over a semiconductor material layer having a first semiconductor material and a disposable gate structure is formed thereupon. A gate spacer is formed around the disposable gate structure and physically exposed portions of the fin-defining mask structures are subsequently removed. The semiconductor material layer is recessed employing the disposable gate structure and the gate spacer as an etch mask to form recessed semiconductor material portions. Embedded planar source/drain stressors are formed on the recessed semiconductor material portions by selective deposition of a second semiconductor material having a different lattice constant than the first semiconductor material. After formation of a planarization dielectric layer, the disposable gate structure is removed. A plurality of semiconductor fins are formed employing the fin-defining mask structures as an etch mask. A replacement gate structure is formed on the plurality of semiconductor fins.

Abstract: We describe the use of a high-quality-factor torsional resonator of microscale dimensions. The resonator has a paddle that is supported by two nanoscale torsion rods made of a very low thermal conductivity material, such as amorphous (“a-”) silicon. The body of the torsion paddle is coated with an infrared-absorbing material that is thin and light weight, but provides sufficient IR absorption for the applications. It may be placed above a reflecting material of similar dimensions to form a quarter wave cavity. Sensing of the response of the paddle to applied electromagnetic radiation provides a measure of the intensity of the radiation as detected by absorption, and the resulting temperature change, in the paddle.

Abstract: A thin-film semiconductor device includes: a substrate; a gate electrode above the substrate; a gate insulation film above the gate electrode; a channel layer above the gate insulation film, the channel layer having a raised part; a channel protection layer over the raised part of the channel layer, the channel protection layer comprising an organic material, and the organic material including silicon, oxygen, and carbon; an interface layer at an interface between a top surface of the raised part of the channel layer and the channel protection layer, and comprises at least carbon and silicon that derive from the organic material; and a source electrode and a drain electrode each provided over a top surface and a side surface the channel protection layer, a side surface of the interface layer, a side surface of the raised part of the channel layer, and a top surface of the channel layer.

Abstract: A silicon carbide substrate, a silicon carbide ingot, and methods for manufacturing the silicon carbide substrate and the silicon carbide ingot capable of improving a yield of a semiconductor device having silicon carbide as constituent material are provided. In the silicon carbide substrate, patterns formed by crossing straight lines extending along the <11-20> direction and being observable by means of an X-ray topography are present at a number density of less than or equal to 0.1 patterns/cm2 on one main surface. As described above, in the silicon carbide substrate, the number density of the crossing patterns present on the main surface is reduced to less than or equal to 0.1 patterns/cm2. Therefore, when the semiconductor device is manufactured with use of a silicon carbide substrate, a lowering of a yield caused by the crossing patterns can be suppressed.

Abstract: According to one embodiment, a thin film transistor includes: a substrate; a semiconductor layer; first and second insulating films; and gate, source and drain electrodes. The semiconductor layer is provided on the substrate. The semiconductor layer is made of an oxide having indium. The semiconductor layer has first and second regions and other region. The first insulating film covers a top face of the other region. The second insulating film covers at least a pair of side surfaces of the semiconductor layer. The second insulating film is formed under a condition different from that for the first insulating film. The gate electrode is provided on the first and second insulating films or below the semiconductor layer. The source and drain electrodes are provided on the first and second regions, respectively. The drain and source electrodes sandwich the pair of the side surfaces of the semiconductor layer.

Abstract: A semiconductor-on-insulator (SOI) substrate comprises a bulk semiconductor substrate, a buried insulator layer formed on the bulk substrate and an active semiconductor layer formed on the buried insulator layer. Impurities are implanted near the interface of the buried insulator layer and the active semiconductor layer. A diffusion barrier layer is formed between the impurities and an upper surface of the active semiconductor layer. The diffusion barrier layer prevents the impurities from diffusing therethrough.

Abstract: The semiconductor device according to the present invention includes a ferroelectric film and an electrode stacked on the ferroelectric film. The electrode has a multilayer structure of an electrode lower layer in contact with the ferroelectric film and an electrode upper layer stacked on the electrode lower layer. The electrode upper layer is made of a conductive material having an etching selection ratio with respect to the materials for the ferroelectric film and the electrode lower layer. The upper surface of the electrode upper layer is planarized.

Abstract: A semiconductor device of one embodiment of the present invention includes a semiconductor, an insulator, a first conductor, and a second conductor. In the semiconductor device, a top surface of the semiconductor has a region in contact with the insulator; a side surface of the semiconductor has a region in contact with the insulator; the first conductor has a first region overlapping with the semiconductor with the insulator positioned therebetween; the first region has a region in contact with the top surface of the semiconductor and a region in contact with the side surface of the semiconductor; the second conductor has a second region in contact with the semiconductor; and the first region and the second region do not overlap with each other.

Abstract: Disclosed are an element isolation structure of a semiconductor device and a method for forming the same, the method including preparing a semiconductor substrate having an inactive region and an active region defined thereon, forming a first hard mask on the semiconductor substrate, exposing the inactive region of the semiconductor substrate by patterning the first hard mask, forming a second hard mask on the entire surface of the semiconductor substrate including the first hard mask, forming a deep trench in the semiconductor substrate by patterning the second hard mask and the semiconductor substrate, removing the patterned second hard mask, forming a shallow trench overlapped with the deep trench by patterning the semiconductor substrate using the first hard mask as a mask, forming an insulation film on the entire surface of the substrate including the shallow trench and the deep trench, filling the shallow trench and the deep trench by forming an element isolation film on the insulation film, and forming

Abstract: A conductive strap structure in lateral contact with a top semiconductor layer is formed on an inner electrode of a deep trench capacitor. A cavity overlying the conductive strap structure is filled a dielectric material to form a dielectric capacitor cap having a top surface that is coplanar with a topmost surface of an upper pad layer. A semiconductor mandrel in lateral contact with the dielectric capacitor cap is formed. The combination of the dielectric capacitor cap and the semiconductor mandrel is employed as a protruding structure around which a fin-defining spacer is formed. The semiconductor mandrel is removed, and the fin-defining spacer is employed as an etch mask in an etch process that etches a lower pad layer and the top semiconductor layer to form a semiconductor fin that laterally wraps around the conductive strap structure. An access finFET is formed employing two parallel portions of the semiconductor fin.

Abstract: A method of forming an integrated circuit including forming a first diffusion area and a second diffusion area on a substrate, wherein the first diffusion area is configured for a first type transistor, the second diffusion area is configured for a second type transistor. The method further includes forming first source and drain regions in the first diffusion area. The method further includes forming second source and drain regions in the second diffusion area. The method further includes forming a gate electrode extending across the first diffusion area and the second diffusion area. The method further includes forming a first metallic layer, a second metallic layer, and a third metallic layer. The first metallic layer is electrically coupled with the first source region. The second metallic layer is electrically coupled with the first and second drain regions. The third metallic layer is electrically coupled with the second source region.