Abstract: A cloud-based ETL system provides error detection, error correction and reporting of data integration flows hosted by cloud services. Categories of errors are identified using one or more checks at different points of a data integration flow and one or more actions selected based at least in part on the error category. A determination can be made whether the error category is fault tolerant and one or more actions can be selected based at least in part on the error fault tolerance to correct the error, restart a flow, or generate a notification assisting a user to correct the error.

Abstract: Techniques to cause a point-to-point link between system components to engage in a negotiation process that may lead to the link transitioning from an active state in which data may be transmitted between system components to a low power state where data may not be transmitted. The negotiation process may occur between each pair of nodes within an electronic system that are interconnected via point-to-point link. The negotiation may ensure that there are no pending transactions or transactions that may occur within an upcoming period of time. Through this negotiation each component acknowledges and agrees to transition the link to the low power state.

Abstract: The present invention relates to a method of transmitting and a method of receiving signals and corresponding apparatus. One aspect of the present invention relates to an efficient L1 signaling method for an efficient transmitter and an efficient receiver using the efficient L1 signaling method for an efficient cable broadcasting.

Abstract: Systems and methods for latches are presented. In one embodiment a system includes scan in propagation component, data propagation component, and control component. The scan in propagation component is operable to select between a scan in value and a recirculation value. The data propagation component is operable to select between a data value and results forwarded from the scan in propagation component, wherein results of the data propagation component are forwarded as the recirculation value to the scan in propagation component. The control component is operable to control an indication of a selection by the scan in propagation component and the data propagation component.

Abstract: A Forward Error Correction (FEC) decoder is provided, for example including a Layered Low Density Parity Check (LDPC) component. In an implementation, power consumption of the LDPC decoder is minimized with minimal to no impact on the error correction performance. This is achieved, in an implementation, by partially or fully eliminating redundant operations in the iterative process.

Abstract: A method of writing data includes receiving a data page to be stored in a data storage device and initiating an encode operation to encode the data page. The encode operation generates first encoded data and a first portion of the first encoded data is stored to the first physical page of the data storage device. The method includes initiating storage of a second portion of the first encoded data to a second physical page of the data storage device. The method also includes initiating a decode operation to recover the data page. The decode operation uses a representation of the first portion of the first encoded data that is read from the first physical page without using any data from the second physical page.

Abstract: A method, system and memory controller are provided for implementing ECC (Error Correction Codes) control to provide enhanced endurance and data retention of flash memories. The memory controller includes a VT (threshold voltage) monitor to determine VT degradation of cells and blocks; the VT monitor configured to store information about the determined VT degradation; a first ECC engine having a first level of ECC capability; a second ECC engine having a second level of ECC capability, the second level higher than the first level, the second ECC engine having a longer latency than the first ECC engine; a logic to issue a read request to a particular cell/block, and, using the determined VT degradation, use the first ECC engine if the determined VT degradation is less than a threshold and to use the second ECC engine if the determined VT degradation is above the threshold.

Abstract: A hard-decision decoding method includes performing operations necessary for first updating of a check node while loading data, which is input to a decoder, to an input buffer; first updating the check node by using a result of the performing of the operations after storing data, corresponding to one codeword, to the input buffer; and performing low-density parity check (LDPC) decoding by using a result of the first updating of the check node.

Abstract: A method for implementing multi standard programmable low-density parity check decoder in a receiver is provided. The method includes (i) generating, by a control signal generation unit, pre computed control signals associated with a h-matrix, (ii) obtaining, by a control signal storage unit of a hardware decoder unit, the pre computed control signals associated with the h-matrix, (iii) obtaining, by a LLR memory fetch & data align unit, LLR bytes from a LLR memory unit, (iv) rotating, by a rotation and aligning unit, the LLR bytes to obtain aligned valid LLR bytes, (v) processing, by the processing element unit, the aligned valid LLR bytes to obtain an output data, and (vi) decoding, the h-matrix associated with at least one standard and code rates based on the pre computed control signals.

Abstract: Various embodiments provide a method for processing encoded data bits transmitted over a lossy communication channel. In some embodiments, the method receives the encoded data bits over the communication channel, the encoded data bits including redundant data units; decodes the encoded data bits at an error correction decoder, wherein the recovery of lost data is implemented at the error correction decoder using at least one of the redundant data units; determining if at least one data bit is unable to be recovered due to the decoder finding a plurality of candidate bit values for the at least one data bit; receives information relating to the transmitter; analyzing the plurality of candidate bit values to exclude at least one of the candidate bit values for the at least one data bit using information relating to the transmitter; and resolves the at least one data bit based on the analysis.

Abstract: Provided are methods, systems, and apparatus for error detection of bits of a data packet received at a receiver unit by detecting corrupted data bits.

Abstract: A data processing method adapted for a rewritable non-volatile memory module is provided. The method includes receiving a first data stream and performing an error-correction encoding procedure on the first data stream to generate an original error checking and correcting (ECC) code corresponding to the first data stream. The method also includes converting the original ECC code into a second ECC code according to a second rearrangement rule, and the original ECC code is different from the second ECC code. The method further includes respectively writing the first data stream and the second ECC code into a data bit area and an error-correction code bit area of the same or different physical programming units in the rewritable non-volatile memory module.

Abstract: Provided are a data transmission apparatus and a method for the data transmission apparatus to transmit a plurality of packets constituting transmission data to a receiving end. The data transmission apparatus for transmitting a plurality of packets constituting transmission data to a receiving end includes a packet-specific weight calculator configured to calculate packet-specific weights of respective transmission-scheduled original packets at a current time point among the plurality of packets, a packet converter configured to generate one or more error recovery packets from the original packets according to the calculated packet-specific weights, and a transmitter configured to transmit the error recovery packets to the receiving end using a plurality of sessions capable of transmission.

Abstract: Embodiments of the present invention provide a video data transmission processing method, a video data sending processing method, an apparatus, and a network system. The data transmission processing method includes: receiving a source stream sent from a source transmission network to a target transmission network; performing, according to respective packet loss rates of the source transmission network and the target transmission network as well as error tolerance aid information corresponding to the source stream, error tolerance coding processing on the source stream to obtain an error tolerance stream; and sending the obtained error tolerance stream to the target transmission network.

Abstract: A method begins by a dispersed storage (DS) processing module generating a data object identifier for data to be stored in a dispersed storage network (DSN) and partitioning the data into a plurality of data partitions based on a set of retrieval preferences and data boundary information. For a data partition, the method continues with the DS processing module dispersed storage error encoding the data partition to produce a plurality of sets of encoded data slices and generating a plurality of sets of DSN addresses for the plurality of sets of encoded data slices, wherein a DSN address of the plurality of sets of DSN addresses includes a representation of the data object identifier, a representation of one or more retrieval preferences of the set of retrieval preferences, a representation of a corresponding portion of the data boundary information, and dispersed storage addressing information.

Abstract: Embodiments of a jitter detection circuit are disclosed that may allow for detecting both cycle and phase jitter in a clock distribution network. The jitter detection circuit may include a phase selector, a data generator, a delay chain, a logic circuit, and clocked storage elements. The phase selector may be operable to select a clock phase to be used for the launch clock, and the data generator may be operable to generate a data signal responsive to the launch clock. The delay chain may generate a plurality of outputs dependent upon the data signal, and the clocked storage elements may be operable to capture the plurality of outputs from the delay chain, which may be compared to expected data by the logic circuit.

Abstract: A method for reading data from a block of a flash memory is provided, where the block includes a plurality of pages and at least one parity page, each of the pages includes a plurality of sectors used for storing data and associated row parities, each of the sectors of the parity page is used to store a column parity. The method includes: reading data from a specific page of the pages; decoding the data of the specific page; and when a specific sector of the specific page fails to be decoded, sequentially reading all original data of the pages and the parity page, and performing error correction upon the specific sector according to at least a portion of the original data of the pages and the parity page corresponding to the specific sector.

Abstract: A memory system includes: a first non-volatile memory used for storing data to be accessed in block units; a second non-volatile memory used for storing data to be accessed in word units in random accesses to the second non-volatile memory; and a control section configured to control operations of the first and second non-volatile memories, wherein error correction codes to be applied to data stored in the second non-volatile memory are held in the first non-volatile memory.

Abstract: According to one embodiment, a controller includes a generator and a creator. The generator generates a channel matrix by counting a number of times a combination of a correct bit value and a read level appears for each bit forming a decoded first frame, based on readout data indicating a read level of each of a plurality of bits forming a frame and the decoded frame. The creator creates a table by statistically calculating a likelihood of a correct bit value of each read level based on the channel matrix.

Abstract: Disclosed is a vehicle data abnormality determination device including a storage unit for pre-storing a 2-byte remainder term which is a result of a CRC arithmetic operation on a target area for arithmetic operations in a predetermined memory area, and an arithmetic operation unit for performing a CRC arithmetic operation while including the 2-byte remainder term in this CRC arithmetic operation. Because when performing the CRC arithmetic operation, the vehicle data abnormality determination device performs the CRC arithmetic operation while including the 2-byte remainder term in this CRC arithmetic operation after performing an arithmetic operation on the target area, the vehicle data abnormality determination device always makes the computed result be zero when the data has not been falsified, and can detect whether or not the data has been falsified easily and properly.