Abstract: A method begins by a processing module dispersed storage error encoding fundamental component data of data in accordance with dispersed storage error coding parameters to produce a plurality of sets of encoded data slices, wherein the data includes the fundamental component data and enhancement component data. The method continues with the processing module transmitting a set of the plurality of sets of encoded data slices and transmitting a corresponding portion of the enhancement component data substantially concurrently with the transmitting of the set of the plurality of sets of encoded data slices.

Abstract: A method of writing data includes receiving a data page to be stored in a data storage device and initiating an encode operation to encode the data page. The encode operation generates first encoded data and a first portion of the first encoded data is stored to the first physical page of the data storage device. The method includes initiating storage of a second portion of the first encoded data to a second physical page of the data storage device. The method also includes initiating a decode operation to recover the data page. The decode operation uses a representation of the first portion of the first encoded data that is read from the first physical page without using any data from the second physical page.

Abstract: According to one embodiment, a storage device includes a first encoder, a storage medium, a second encoder, and a wireless communication unit. The first encoder generates a first codeword including a first information part corresponding to at least a part of write data, and a first redundant part used to correct the first information part. The storage medium stores the first codeword. The second encoder generates a second redundant part used to correct a second information part corresponding to the first codeword or the first information part. The wireless communication unit wirelessly transmits the second redundant part to an external storage device.

Abstract: A method and apparatus are provided for modulating a binary source sequence including of a plurality of source words to generate modulated symbols. The method implements error-correction encoding of the plurality of source words, implementing one or more encoding modules, each implementing a separate error-correction code to generate a plurality of code words, the source words being encoded in series. The code words are interlaced to generate an interlaced sequence. The interlaced sequence is differentially modulated to generate modulated symbols. Each code word is broken down into at least one group with a number of bits equal to the base-2 logarithm of a number of states of a modulation implemented by the step of differentially modulating. The interlacing step distributes the groups such that two adjacent groups in the interlaced sequence belong to separate code words.

Abstract: According to one embodiment, a semiconductor memory device includes first to fifth units. The first unit compares first data being write target data before write in a memory, with second data written in the memory and then read out. The second unit stores the first data if a data comparison result indicates mismatch. The third unit stores a write address corresponding to the write target data if the data comparison result indicates mismatch. The fourth unit compares a read address corresponding to read target data with an address stored in the third unit. The fifth unit selects data read out from the memory in accordance with the read address as the read target data if a address comparison result indicates mismatch, and selects data read out from the second unit as the read target data if the address comparison result indicates match.

Abstract: This invention permits selectively bypasses serial scan chains. Constant or low toggle data is directed to the bypassed serial scan chain, thus reducing power consumption. The number and identity of serial scan chains bypassed during a particular test can be changed dynamically dependent upon the semiconductor process variations of a particular integrated circuit. This enables an optimal test to be preformed for integrated circuits having differing semiconductor process variations.

Abstract: In general, techniques are described for efficiently and transparently partitioning a physical address space of a DRAM part lacking dedicated error protection circuitry to supply addressable error protection bytes for use in detecting and/or correcting bit errors elsewhere present in the physical address space. In one example, a network device includes a DRAM and a memory controller that receives a write command to write data to the DRAM. An address translation module of the memory controller logically partitions the DRAM to define a plurality of physically addressable sections that includes an error protection section for storing error protection bits and one or more data storage sections. The memory controller defines a contiguous logical address space representing the data storage sections. A DRAM controller of the network device communicates with the DRAM to store the data to one of the data storage sections in accordance with the contiguous logical address space.

Abstract: Embodiments of the present invention provide a system for secure error detection and synchronous data tagging for high-speed data transfer (e.g., utilizing a set of SSD memory disk units). Specifically, in a typical embodiment, the system comprises a SSD memory disk unit in communication with a device driver. A first encoded communication stream will be generated with the device driver and sent via PCI-based channel (e.g., full duplex) to the SSD memory disk unit. The stream is received, synchronized, and decoded on the SSD memory disk unit. In turn, the SSD memory disk unit can generate and send a second encoded communication steam to the device driver.

Abstract: A method of handling a retransmission of a hybrid automatic repeat request scheme for a receiver in a communication system is disclosed. The method comprises receiving a first payload from a transmitter in the communication system, and feeding back a resource index to the transmitter, to indicate a size for a second payload in the next reception, when the receiver is unsuccessful to decode the first payload into a plurality of information bits, wherein the transmitter encodes the plurality of information bits into the first payload by using an error correction code.

Abstract: A memory device is configured to generate a signal having a temperature compensation function. The device includes a mode register configured to store error detection and correction (EDC) mode data, and an EDC pattern generator configured to receive pattern information and period information included in the mode data and to generate an EDC pattern signal based on the pattern information and the period information. The EDC pattern signal is a periodic signal obtained by repeating a signal pattern based on the pattern information at a periodic rate corresponding to a signal period based on the period information. In some cases, the EDC pattern signal may be disabled during a portion of the signal period.

Abstract: A method of decoding a block with a Soft Output Viterbi Algorithm (SOVA) using a trellis representation and a sliding window wherein each position of the sliding window has a path determination stage at one end of the sliding window and a symbol decision stage at another end of the sliding window is disclosed. The method comprises determining, for each path determination stage and for each node of the path determination stage, a surviving path (including a surviving path input symbol and a surviving decision stage node) and a concurrent path (including a concurrent path input symbol and a concurrent decision stage node) based on path metrics. A path metric disparity value is calculated and stored for each node.

Abstract: A nonvolatile semiconductor memory outputs the first parity flag corresponding to the error-corrected read data from the second input/output pin in synchronization with the error-corrected read data in the data buffer outputted from the first input/output pin.

Abstract: The disclosed device performs a control of generating a test pattern for the delay test of LSI. The input pattern control circuit counts a cycle number of an input pattern supplied to a test object circuit, and stops supply of the input pattern to the test object circuit when the cycle number of the input pattern coincides with a certain count number. The scan control circuit receives a control signal from the input pattern control circuit, and supplies a scan shift signal to the test object circuit to shift a scan chain in the test object circuit.

Abstract: Subject matter disclosed herein relates to error protection of data stored in and/or read from a memory device.

Abstract: A first circuit has a reset input. A second circuit is configured to be reset and provide an output. A test circuit is configured to test the first circuit and second circuit. The test circuit is configured such that a fault with the first circuit and said second circuit is determined in dependence on an output of the first circuit.

Abstract: A memory system includes: a first non-volatile memory used for storing data to be accessed in block units; a second non-volatile memory used for storing data to be accessed in word units in random accesses to the second non-volatile memory; and a control section configured to control operations of the first and second non-volatile memories, wherein error correction codes to be applied to data stored in the second non-volatile memory are held in the first non-volatile memory.

Abstract: A parallel operation processing apparatus and method using a Single Instruction Multiple Data (SIMD) processor are provided. The parallel operation processing apparatus may combine input data of source nodes in a current column with input data of source nodes in a previous column, and may store the combined input data.

Abstract: A data processing system having a first processor, a second processor, a local memory of the second processor, and a built-in self-test (BIST) controller of the second processor which performs BIST memory accesses on the local memory of the second processor and which includes a random value generator is provided. The system can perform a method including executing a secure code sequence by the first processor and performing, by the BIST controller of the second processor, BIST memory accesses to the local memory of the second processor in response to the random value generator. Performing the BIST memory accesses is performed concurrently with executing the secure code sequence.

Abstract: A first decoder performs decoding on each data set in a first plurality of data sets using a first code; each data set in the first plurality is stored on a different NAND Flash chip. It is determined if the first decoding is successful; if not, a second decoder performs a second decoding on each data set in a second plurality of data sets using a second code; each data set in the second plurality includes at least some data, after the first decoding using the first code, from each data set in the first plurality. The first decoder performs a third decoding on each data set in the first plurality using the first code, where each data set in the first plurality includes at least some data, after the second decoding using the second code, from each data set in the second plurality.

Abstract: When an update disable signal is at an inactivation level, a latch signal is activated in accordance with an active signal and a mode register set signal. When the update disable signal is at an activation level, the latch signal is activated in accordance with the active signal while being not activated in accordance with the mode register set signal. Based on the latch signal, the address signal is latched. Based on the latched address signal, an internal test signal is generated. With this structure, a target chip can be selectively controlled simply by activating the update disable signal in the target chip.