Patents Examined by Pablo Huerta
  • Patent number: 9672918
    Abstract: A semiconductor memory includes a first selection transistor and a second selection transistor on one end of a memory string. The first selection transistor includes a channel region in a semiconductor substrate, a channel region in a semiconductor pillar, and a gate electrode connected to a first line. The second selection transistor includes a channel region in the semiconductor pillar and a gate electrode connected to a second line. The first line is connected to a first voltage circuit, and the second line is connected to a second voltage circuit.
    Type: Grant
    Filed: February 27, 2015
    Date of Patent: June 6, 2017
    Assignee: kabushiki Kaisha Toshiba
    Inventor: Toshifumi Hashimoto
  • Patent number: 9570195
    Abstract: A circuit and method for memory characterization. The circuit includes first and second programmable delay lines, address and data registers, an output register and a finite state machine controller. The finite state machine controller supplies an address to the address register, data to the data register and controlling a delay of the first programmable delay line and the second programmable delay line in at least one predetermined sequence to determine an operating characteristic of the memory to be tested. The programmable delay lines may be connected as a ring oscillator. Determination of the frequency of the ring oscillator via a counter determines the delay of the delay line. The programmable delay lines, the address register and data registers, the output register, the finite state machine controller and the memory to be tested are preferably constructed on a same semiconductor substrate.
    Type: Grant
    Filed: March 2, 2015
    Date of Patent: February 14, 2017
    Assignee: TEXAS INSTRUMENTS INCORPORATED
    Inventors: Abhijith Ramesh Kashyap, Shrikrishna Pundoor
  • Patent number: 9520559
    Abstract: A memory device includes a first metal layer and a first metal oxide layer coupled to the first metal layer. The memory device includes a second metal oxide layer coupled to the first metal oxide layer and a second metal layer coupled to the second metal oxide layer. The formation of the first metal oxide layer has a Gibbs free energy that is lower than the Gibbs free energy for the formation of the second metal oxide layer.
    Type: Grant
    Filed: October 2, 2015
    Date of Patent: December 13, 2016
    Assignee: 4D-S PTY, LTD
    Inventor: Dongmin Chen
  • Patent number: 9496050
    Abstract: Various embodiments include apparatus, systems, and methods having multiple dies arranged in a stack in which the dies or a logic chip in communication with the dies stores a flag for indicating whether a threshold number of cells of the dies have failed during test operations.
    Type: Grant
    Filed: May 22, 2013
    Date of Patent: November 15, 2016
    Assignee: Micron Technology, Inc.
    Inventors: Boon Hor Lam, Dennis Montierth
  • Patent number: 9478281
    Abstract: A variable resistance memory apparatus and a method of manufacturing the same are provided. The variable resistance memory apparatus includes a plurality of memory cells. Each of the memory cells includes a plurality of data storage regions. The plurality of data storage regions have different widths from each other.
    Type: Grant
    Filed: January 9, 2014
    Date of Patent: October 25, 2016
    Assignee: SK Hynix Inc.
    Inventor: Min Seok Son
  • Patent number: 9466341
    Abstract: A sense amplifier circuit includes a first transistor, a second transistor, a third transistor, a fourth transistor, a first resistive device, a second resistive device, a fifth transistor and a sixth transistor. A gate of the first transistor is coupled to a drain of the fourth transistor. A drain of the first transistor is coupled to a gate of the fourth transistor. A gate of the second transistor is coupled to a drain of the third transistor. A drain of the second transistor is coupled to a gate of the third transistor. The first resistive device is coupled to a first data line and at least the drain of the first transistor or third transistor. The second resistive device is coupled to a second data line and at least the drain of the second transistor or the fourth transistor. The sources of the third and fourth transistor are coupled together.
    Type: Grant
    Filed: August 6, 2015
    Date of Patent: October 11, 2016
    Assignee: TAIWAN SEMICONDUCTOR MANUFATURING COMPANY, LTD.
    Inventor: Hyun-Sung Hong
  • Patent number: 9466345
    Abstract: A semiconductor memory device according to an embodiment of the present invention includes a memory block, a driving circuit performing a program operation on memory cells and a voltage detector generating a detection signal when an external power supply voltage is reduced to less than a reference voltage level. The driving circuit discharges a voltage applied to a drain selection line during the program operation in response to the detection signal.
    Type: Grant
    Filed: December 16, 2013
    Date of Patent: October 11, 2016
    Assignee: SK Hynix Inc.
    Inventor: Se Kyoung Choi
  • Patent number: 9455016
    Abstract: A semiconductor device includes a memory cell array including a normal memory cell array and a redundancy memory cell array, a normal refresh counter suitable for generating a normal address for performing a refresh operation to the normal memory cell array with a first period during a refresh mode and a redundancy refresh counter suitable for generating a redundancy address for performing a refresh operation to the redundancy memory cell with a second period shorter than the first period.
    Type: Grant
    Filed: December 15, 2013
    Date of Patent: September 27, 2016
    Assignee: SK Hynix Inc.
    Inventor: Jong-Yeol Yang
  • Patent number: 9443596
    Abstract: A non-volatile memory device includes a memory cell array and a voltage generator. The memory cell array has a plurality of cell strings in which a plurality of memory cells are connected with each other in series between a string select transistor and a ground select transistor. The voltage generator generates a program voltage, a first pass voltage, and a second pass voltage. A first boost channel voltage applied when programming an outermost memory cell from among the memory cells of each of non-selected cell strings of the cell strings is lower than a second boost channel voltage applied when programming one of remaining memory cells except for the outermost memory cell. The non-volatile memory device prevents programming disturb caused by hot carrier injection.
    Type: Grant
    Filed: February 27, 2014
    Date of Patent: September 13, 2016
    Assignee: Samsung Electronics Co., Ltd.
    Inventor: Chang-Hyun Lee
  • Patent number: 9424954
    Abstract: A semiconductor package includes first and second slave chips stacked vertically; and a master chip connected to the first and second slave chips, each of the slave chips including, a plurality of memory blocks, and a redundancy block, and the master chip including, a fuse block configured to repair a defective memory block detected from the first slave chip and a defective memory block detected from the second slave chip by using the redundancy block of the first slave chip and the redundancy block of the second slave chip, respectively, and a block selection circuit configured to, connect the redundancy blocks of the first and second slave chips, one or more non-defective ones of the plurality of memory blocks of the first slave chip, and one or more non-defective ones of the plurality of memory blocks of the second slave chip to an input/output circuit.
    Type: Grant
    Filed: January 8, 2014
    Date of Patent: August 23, 2016
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Taek-Sung Kim, Sangbo Lee, SoonYong Hur
  • Patent number: 9418742
    Abstract: A nonvolatile semiconductor memory device includes a first string including a first number of memory cells connected in series each storing therein information in a nonvolatile manner; and a second string including a second number of memory cells connected in series each storing therein information in a nonvolatile manner, wherein the second number is smaller than the first number.
    Type: Grant
    Filed: September 27, 2013
    Date of Patent: August 16, 2016
    Assignee: PS4 LUXCO S.A.R.L.
    Inventors: Naoharu Shinozaki, Masao Taguchi, Takahiro Hatada, Satoru Sugimoto, Satoshi Sakurakawa
  • Patent number: 9418749
    Abstract: A nonvolatile memory device performs a read operation comprising first and second intervals. In the first interval the device applies a turn-on voltage to string selection lines and ground selection lines connected to the string selection transistors and the ground selection transistors, respectively. In the second interval, the device applies a turn-off voltage to unselected string selection lines and unselected ground selection lines while continuing to apply the turn-on voltage to a selected string selection line and a selected ground selection line. In both the first and second intervals, the device applies a first read voltage to a selected wordline connected to memory cells to be read by the read operation and applying a second read voltage to unselected wordlines among connected to memory cells not to be read by the read operation.
    Type: Grant
    Filed: October 12, 2015
    Date of Patent: August 16, 2016
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Sang-Wan Nam, Won-Taeck Jung
  • Patent number: 9412441
    Abstract: A semiconductor memory device includes a cell string including dummy memory cells and a plurality of memory cells in which n bit data is stored, and a peripherial circuit configured to store the n bit data in first memory cells, among the memory cells, store n?1 bit data in the rest of second memory cells, and store data which is not stored in the second memory cells in at least one of the dummy memory cells, among the dummy memory cells.
    Type: Grant
    Filed: January 4, 2016
    Date of Patent: August 9, 2016
    Assignee: SK HYNIX INC.
    Inventor: Hee Youl Lee
  • Patent number: 9412472
    Abstract: Apparatuses and methods involving the determination of soft data from hard reads are provided. One example method can include determining, using a hard read, a state of a memory cell. Soft data is determined based, at least partially, on the determined state.
    Type: Grant
    Filed: November 13, 2015
    Date of Patent: August 9, 2016
    Assignee: Micron Technology, Inc.
    Inventors: Sivagnanam Parthasarathy, Patrick R. Khayat, Mustafa N. Kaynak
  • Patent number: 9406363
    Abstract: A memory device includes wordline decoder circuits that share components between adjacent memory blocks. The wordline decoder circuits include multiple levels, where at least one level is split, driving half of the wordlines in one adjacent memory block and driving half of the wordlines in another adjacent memory block. Memory blocks have every other wordline coupled to one adjacent decoder circuit, and the remaining wordlines coupled to another adjacent decoder circuit.
    Type: Grant
    Filed: April 25, 2014
    Date of Patent: August 2, 2016
    Assignee: Micron Technology, Inc.
    Inventors: Gerald Barkley, Efrem Bolandrina, Daniele Vimercati
  • Patent number: 9406384
    Abstract: Devices, circuitry, and methods for improving matching between semiconductor circuits are shown and described. Measuring a difference in matching between semiconductor circuits may be performed with a test current generator and test current measurement circuit, and adjusting a threshold voltage of a semiconductor component of at least one circuit until the difference between the circuits is at a desired difference may be performed with a program circuit.
    Type: Grant
    Filed: November 28, 2012
    Date of Patent: August 2, 2016
    Assignee: Micron Technology, Inc.
    Inventors: Daniele Vimercati, Andrea Marmiroli
  • Patent number: 9396797
    Abstract: A program method of a nonvolatile memory device includes loading first word line data to be stored in first memory cells connected to a first word line and second word line data to be stored in second memory cells connected to a second word line; setting up upper bit lines according to the first word line data; turning off bit line sharing transistors after the upper bit lines are set up; setting up lower bit lines according to the second word line data; performing a first program operation on the first memory cells using the upper bit lines; turning on the bit line sharing transistors; and performing a second program operation on the second memory cells using the lower bit lines. The bit line sharing transistors electrically connect the upper bit lines and the lower bit lines in response to a bit line sharing signal.
    Type: Grant
    Filed: January 9, 2014
    Date of Patent: July 19, 2016
    Assignee: Samsung Electronics Co., Ltd.
    Inventor: Dongku Kang
  • Patent number: 9384785
    Abstract: Subject matter disclosed herein relates to a memory device, and more particularly to a multi-channel memory device and methods of selecting one or more channels of same.
    Type: Grant
    Filed: December 2, 2013
    Date of Patent: July 5, 2016
    Assignee: Micron Technology, Inc.
    Inventor: Emanuele Confalonieri
  • Patent number: 9385118
    Abstract: A capacitor array includes a plurality of capacitor cell structures. The capacitor cell structures of the plurality of cell structures each includes a first capacitor electrode, a second capacitor electrode over the first capacitor electrode, a third capacitor electrode adjacent to first sidewalls of the first and second capacitor electrodes, a fourth capacitor electrode adjacent to second sidewalls of the first and second capacitor electrodes, and a fifth capacitor electrode adjacent to the fourth capacitor electrode.
    Type: Grant
    Filed: April 22, 2015
    Date of Patent: July 5, 2016
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Yvonne Lin, Wen-Ting Chu
  • Patent number: 9384808
    Abstract: An address input circuit of a semiconductor device includes: an address latch unit configured to generate latch addresses, by latching addresses sequentially provided by an external, according to a command decoding signal, wherein latch timings of each of the addresses are adjusted differently from one another; and a command decoder configured to decode a command provided from the external and generate the command decoding signal.
    Type: Grant
    Filed: December 16, 2013
    Date of Patent: July 5, 2016
    Assignee: SK hynix Inc.
    Inventors: Young Ju Kim, Kwan Weon Kim, Dong Uk Lee