Patents Examined by Pamela Perkins
  • Patent number: 7759246
    Abstract: A semiconductor device includes a first semiconductor chip (5) having a first terminal (7) on one surface, a second semiconductor chip (1a) which is larger than the first semiconductor chip (5) and on which the first semiconductor chip (5) is stacked and which has a second terminal (3) on one surface, an insulating layer (10) formed on a second semiconductor chip (1a) to cover the first semiconductor chip (5), a plurality of holes (10a) formed in the insulating layer (10) on at least a peripheral area of the first semiconductor chip (5), a via (11a) formed like a film on inner peripheral surfaces and bottom surfaces of the holes (10a) and connected electrically to the second terminal (3) of the second semiconductor chip (1a), a wiring pattern (11b) formed on an upper surface of the insulating layer (10), and an external terminal (14) formed on the wiring pattern (11b).
    Type: Grant
    Filed: June 30, 2006
    Date of Patent: July 20, 2010
    Assignee: Fujitsu Semiconductor Limited
    Inventors: Hirohisa Matsuki, Yoshitaka Aiba, Mitsutaka Sato, Tadahiro Okamato
  • Patent number: 7078311
    Abstract: There is provided a capacitor embedded in a substrate having a small thickness and requiring only a small space for short connection lines. The substrate-embedded capacitor comprises a substrate having an opening, a first conductive layer on the substrate, a dielectric layer on the first conductive layer, a second conductive layer on the dielectric layer, and an insulating layer formed on the second conductive layer and having an opening. In the substrate-embedded capacitor, the first conductive layer and the second conductive layer are exposed through the openings in the substrate and the insulating layer, respectively.
    Type: Grant
    Filed: December 22, 2003
    Date of Patent: July 18, 2006
    Assignee: Shinko Electric Industries Co., Ltd.
    Inventors: Mitsutoshi Higashi, Hideaki Sakaguchi, Hiroko Koike
  • Patent number: 7041610
    Abstract: In order to achieve temperature distribution, in particular a homogeneous temperature distribution in, for example, a substrate during a thermal treatment process of said substrate, a method is disclosed for the thermal treatment of substrates, in particular semi-conductor wafers, in a process chamber comprising at least one temperature distribution influencing element located in the process chamber. During thermal treatment, the spatial arrangement of the element is altered relative to the substrate and/or to the process chamber. A device for the thermal treatment of substrates in a process chamber is also disclosed, comprising at least one temperature distribution influencing element located in a process chamber wherein a device is provided in order to alter the spatial arrangement of the element relative to the substrate and/or to the process chamber during the thermal treatment process.
    Type: Grant
    Filed: October 19, 2000
    Date of Patent: May 9, 2006
    Assignee: Steag RTP Systems GmbH
    Inventors: Andreas Tillmann, Uwe Kreiser
  • Patent number: 6939780
    Abstract: Trench isolated integrated circuit devices are fabricated by forming a trench including sidewalls in an integrated circuit substrate, and forming a lower device isolation layer in the trench and extending onto the trench sidewalls. The lower device isolation layer includes grooves therein, a respective one of which extends along a respective one of the sidewalls. An upper device isolation layer is formed on the lower device isolation layer and in the grooves. Trench isolated integrated circuit devices include an integrated circuit substrate including a trench having sidewalls and a lower device isolation layer in the trench and extending onto the trench sidewalls. The lower device isolation layer includes grooves therein, a respective one of which extends along a respective one of the sidewalls. An upper device isolation layer is provided on the lower device isolation layer and in the grooves.
    Type: Grant
    Filed: June 24, 2003
    Date of Patent: September 6, 2005
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Jae-Sun Yun, Jin-Hyun Shin
  • Patent number: 6887725
    Abstract: A micro electron gun that is capable of extracting electrons from a semiconductor utilizing a quantum size effect and that can be mounted individually for each of pixels is disclosed, as well as a picture display apparatus using such electron guns which is high in quantum efficiency, of high brightness and thin, as well as methods of manufacture thereof. Conduction electrons from a n-type semiconductor substrate (2) are accelerated under an electric field through a layer or layers (4) of quantum size effect micro particles (3) formed on surfaces of the n-type semiconductor substrate (2) and passed therethrough without undergoing phonon scattering, so that they when arriving at an electrode (5) may possess an amount of energy not less than the work function of the electrode (5) and are thus allowed to spring out into a vacuum.
    Type: Grant
    Filed: September 23, 2003
    Date of Patent: May 3, 2005
    Assignee: Japan Science and Technology Agency
    Inventors: Shunri Oda, Xinwei Zhao, Katsuhiko Nishiguchi
  • Patent number: 6881613
    Abstract: An electronic component package and method of fabrication is provided. The electronic component package includes a ceramic substrate and a plurality of bonding pads formed on the substrate, each pad forming an interface with the ceramic. Formed on the bonding pads is a bonding material, and a plurality of electrical leads are secured to corresponding pads by the bonding material. A layer of adhesive is formed over at least the interfaces between the pads and ceramic.
    Type: Grant
    Filed: October 8, 2002
    Date of Patent: April 19, 2005
    Assignee: Agere Systems Inc
    Inventors: Gaurav Agrawal, Jesse W. Booker, Christopher E. Sosh
  • Patent number: 6730595
    Abstract: This invention aims to provide a protecting method for a semiconductor wafer which can prevent breakage of a semiconductor wafer even when a semiconductor wafer is thinned to a thickness of 200 &mgr;m or less, and a surface protecting adhesive film for a semiconductor wafer used in the protecting method.
    Type: Grant
    Filed: December 6, 2001
    Date of Patent: May 4, 2004
    Assignee: Mitsui Chemicals, Inc.
    Inventors: Yoshihisa Saimoto, Yasuhisa Fujii, Makoto Kataoka, Kentaro Hirai, Hideki Fukumoto, Takanobu Koshimizu
  • Patent number: 6720247
    Abstract: A low-k dielectric layer (104) is treated with a dry H2 plasma pretreatment to improve patterning. Resist poisoning occurs due to an interaction between low-k films (104), such as OSG, and DUV resist (130). The H2 plasma pre-treatment is performed to either pretreat a low-k dielectric (104) before forming the pattern (130) or during a rework of the pattern (130).
    Type: Grant
    Filed: October 25, 2001
    Date of Patent: April 13, 2004
    Assignee: Texas Instruments Incorporated
    Inventors: Brian K. Kirkpatrick, Michael Morrison, Andrew J. McKerrow, Kenneth J. Newton, Dirk N. Anderson
  • Patent number: 6696336
    Abstract: A method used during the formation of a semiconductor device comprises providing a wafer substrate assembly comprising a plurality of digit line plug contact pads and capacitor storage cell contact pads which contact a semiconductor wafer. A dielectric layer is provided over the wafer substrate assembly and etched to expose the digit line plug contact pads, and a liner is provided in the opening. A portion of the digit line plug is formed, then the dielectric layer is etched again to expose the capacitor storage cell contact pads. A capacitor bottom plate is formed to contact the storage cell contact pads, then the dielectric layer is etched a third time using the liner and the bottom plate as an etch stop layer. A capacitor cell dielectric layer and capacitor top plate is formed which provides a double-sided container cell. An additional dielectric layer is formed, then the additional dielectric layer, cell top plate, and the cell dielectric are etched to expose the digit line plug portion.
    Type: Grant
    Filed: May 14, 2001
    Date of Patent: February 24, 2004
    Assignee: Micron Technology, Inc.
    Inventors: Scott J. DeBoer, Ronald A. Weimer, John T. Moore
  • Patent number: 6686259
    Abstract: In a method for manufacturing a solid state image pick up device capable of improving gettering efficiency a semiconductor substrate having a front side on which a solid state image pick-up device may be formed, and a rear side opposite to the front side is provided. Subsequently, a polysilicon layer including impurities for gettering having a predetermined concentration is formed on the rear side of the semiconductor substrate. Next, a predetermined thickness of the polysilicon layer including the impurities for gettering is oxidized, and the impurities for gettering are condensed into the reduced polysilicon layer.
    Type: Grant
    Filed: November 27, 2001
    Date of Patent: February 3, 2004
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Sang-sik Park, Mikio Takagi, Jae-heon Choi, Sang-il Jung, Jun-taek Lee
  • Patent number: 6677232
    Abstract: A method for fabricating a metal conductor in a semiconductor device includes forming a trench in a dielectric layer of the semiconductor device. The method also includes depositing a first conducting material within the trench to form a continuous liner layer within the trench. The liner layer is formed at a first predetermined temperature. The method further includes filling a remaining portion of the trench over the liner layer with a second conducting material at a second predetermined temperature. The second predetermined temperature is greater than the first predetermined temperature.
    Type: Grant
    Filed: November 1, 2001
    Date of Patent: January 13, 2004
    Assignee: Texas Instruments Incorporated
    Inventors: Qi-Zhong Hong, Wei-Yung Hsu, Vincent T. Cordasco
  • Patent number: 6677661
    Abstract: In one aspect, the invention includes a semiconductor fabrication process, comprising: a) providing a substrate; b) forming a layer of silicon nitride over the substrate, the layer having a thickness; and c) enriching a portion of the thickness of the silicon nitride layer with silicon, the portion comprising less than or equal to about 95% of the thickness of the layer of silicon nitride. In another aspect, the invention includes a semiconductor fabrication process, comprising: a) providing a substrate; b) forming a layer of silicon nitride over the substrate, the layer having a thickness; and c) increasing a refractive index of a first portion of the thickness of the silicon nitride layer relative to a refractive index of a second portion of the silicon nitride layer, the first portion comprising less than or equal to about 95% of the thickness of the silicon nitride layer.
    Type: Grant
    Filed: October 28, 1999
    Date of Patent: January 13, 2004
    Assignee: Micron Technology, Inc.
    Inventors: Scott Jeffrey DeBoer, John T. Moore, Mark Fischer, Randhir P. S. Thakur
  • Patent number: 6667223
    Abstract: A method of providing isolation between active areas of memory cells in a memory device having a plurality of isolation trenches (115) separating the active areas, comprising depositing a first insulating material (116) and forming a resist (120) over the first insulating material (116) over at least the trenches (115), leaving a first top portion of the first insulating material (116) exposed. At least a second top portion of the first insulating material (116) is removed, the resist (120) is removed, and a second insulating material (216) is deposited over the wafer (100) to completely fill the isolation trenches (115).
    Type: Grant
    Filed: July 13, 2001
    Date of Patent: December 23, 2003
    Assignee: Infineon Technologies AG
    Inventor: Mihel Seitz
  • Patent number: 6656800
    Abstract: A gate oxide film and a first layer of a multi-layered gate electrode are stacked on a substrate and by a gate prefabrication technique, an oxide layer of an element isolation region is formed in a self-alignment manner using the first layer of the gate electrode as a mask, impurities for a transistor channel control are doped by ion implantation via the first layer of the gate electrode and the gate oxide film, and the doped impurities are activated by a heating step, whereby an impurity profile at the transistor channel portion is precisely formed.
    Type: Grant
    Filed: June 25, 2001
    Date of Patent: December 2, 2003
    Assignee: Kabushiki Kaisha Toshiba
    Inventor: Norihisa Arai
  • Patent number: 6653206
    Abstract: A method of processing a composite member having a structure in which a first member having a separation layer inside is brought into tight contact with a second member. The composite member has a projecting portion at which a peripheral edge of the first member projects outside a peripheral edge of the second member. The method includes a detection step of detecting the projecting portion of the composite member using a sensor and a separation step of starting separating the composite member from the projecting portion detected in the detection step and then separating the composite member into two members at the separation layer.
    Type: Grant
    Filed: July 23, 2001
    Date of Patent: November 25, 2003
    Assignee: Canon Kabushiki Kaisha
    Inventors: Kazutaka Yanagita, Kazuaki Ohmi, Kiyofumi Sakaguchi, Hirokazu Kurisu
  • Patent number: 6649425
    Abstract: A method for reducing sub-threshold leakage during the burn-in procedure for a semi-conductor is disclosed. The method includes applying a back-bias voltage to the device during the burn-in procedure. The back-bias voltage increases the threshold voltage of the semi-conductor device and consequently, reduces the sub-threshold leakage current.
    Type: Grant
    Filed: April 4, 2001
    Date of Patent: November 18, 2003
    Assignee: Sun Microsystems, Inc.
    Inventor: Ban P. Wong
  • Patent number: 6649524
    Abstract: Methods and apparatuses for efficiently forming a homogeneous glass layer having uniform thickness and a homogeneous metal layer having uniform thickness are provided. A workpiece is accommodated in a screened container which is rotatable in a predetermined direction. The workpiece in the container is sprayed with an atomized glass slurry or an atomized metal slurry while the container is rotated in order to form a green glass layer or a green metal layer on the workpiece. Simultaneously, hot air is supplied to the workpiece so as to dry the green glass layer or the green metal layer. Thus, the workpiece, typically a ferrite core, can be provided with a homogeneous layer having a uniform thickness. A method for manufacturing an electronic component using the above-described methods and apparatuses is also provided.
    Type: Grant
    Filed: December 1, 2000
    Date of Patent: November 18, 2003
    Assignee: Murata Manufacturing Co., Ltd.
    Inventor: Shizuharu Watanabe
  • Patent number: 6642133
    Abstract: The invention relates to a transistor that includes a semiconductive layer on an insulator layer. Below the insulator layer is a substrate and a contact is disposed in the insulator layer that originates at the substrate and terminates in the insulator layer. The contact is aligned below the transistor junction. The invention also relates to a process flow that is used to fabricate the transistor. The process flow includes forming the contact by either a spacer etch or a directional, angular etch.
    Type: Grant
    Filed: December 20, 2001
    Date of Patent: November 4, 2003
    Assignee: Intel Corporation
    Inventors: Brian Roberds, Doulgas W. Barlage
  • Patent number: 6635567
    Abstract: Alignment marks (overlay marks or alignment markers) are produced in a semiconductor structure with integrated circuits. Contact holes and alignment trenches are etched into an insulator layer and in each case open out at a first metal layer at their undersides. Metal is deposited into the alignment trenches and the contact holes. With a subsequent chemical mechanical polishing procedure, the metal areas are lowered in the region of the alignment trenches and form profiles for the alignment marks in a second metal layer, which is deposited on the insulator layer.
    Type: Grant
    Filed: January 11, 2001
    Date of Patent: October 21, 2003
    Assignee: Infineon Technologies AG
    Inventors: Eva Ebertseder, Matthias Lehr, Torsten Werneke, Jochen Hanebeck, J├╝rgen Pahlitzsch
  • Patent number: 6632750
    Abstract: Described is a manufacturing method of a semiconductor integrated circuit device by depositing a silicon nitride film to give a uniform thickness over the main surface of a semiconductor wafer having a high pattern density region and a low pattern density region. This is attained by, upon depositing a silicon nitride film over a substrate having a high gate-electrode-pattern density region and a low gate-electrode-pattern density region by using a single-wafer cold-wall thermal CVD reactor, setting a flow rate ratio of ammonia (NH3) to monosilane (SiH4) greater than that upon deposition of a silicon nitride film over a flat substrate.
    Type: Grant
    Filed: July 17, 2001
    Date of Patent: October 14, 2003
    Assignees: Hitachi, Ltd., Hitachi ULSI Systems Co. Ltd.
    Inventors: Hidenori Sato, Yoshiyuki Hayashi, Toshio Ando