Abstract: A lead frame is placed on a lower mold with its non-mounting surface facing upward. An unused portion of a resin tape is supplied between the upper mold and the lower mold. The resin tape is sucked to the upper mold and preheated. A molten resin is injected into a cavity for curing, with the upper and lower molds closed together, and with the lead frame positioned loosely without being tightly clamped between the upper and lower molds. The injected resin presses the lead frame against the resin tape on the upper mold surface. Thus, resin sealing is performed. In this method, the resin tape is kept in close contact with the non-mounting surface of the lead frame and held in a space of the lead frame for resin sealing, so that formation of a cured resin on the bottom surface of the package can be prevented.

Abstract: Surface mount diodes are mass produced by first cutting a metal plate to form a plurality of vertical slits within metal plate. Parallel lines are cut midway between the slits to form wings for the slits. The wings are folded to form the bottoms for surface mounting. Glue is applied over the metal plate to form focusing cups.

Abstract: The present invention discloses a method for forming a gate electrode of a flash memory. A tunnel oxide film is formed on the whole surface of a semiconductor substrate. A conductive film of a floating gate is formed over the resultant structure. A gate insulation film is formed by depositing a TaON film on the conductive film for the floating gate. A conductive film for a control gate is formed on the gates insulation film. The conductive film for the control gate, the gates insulation film, the conductive film for the floating gate and the tunnel oxide film are patterned according to a photolithography process using a gate mask, thereby forming a gate electrode. Thus, the TaON film having a high dielectric constant and a stabilized bonding structure is used as the insulation material between the floating gate and the control gate. As a result, an oxidization reactivity with the floating gate is reduced, and a thickness of an equivalent oxide film is decreased, thereby obtaining a high capacitance.

Abstract: A packaging arrangement is described that utilizes a conductive panel (such as a leadless leadframe) as its base. The conductive panel has a matrix of device areas that each include a plurality of rows of contacts that are located outside of a die area. Tie bars provide support for the various contacts. Some of the tie bars are arranged to extend between adjacent contacts in the same row and some of the tie bars are arranged to extend diagonally between associated contacts in adjacent rows that are not adjacent one another. During packaging, the tie bars can be severed by cutting along lines (e.g. saw streets) that run adjacent the rows after a molding operation. The described panels are particularly useful in packages having three or more rows of contacts.

Abstract: A solid-state memory including an array of magnetic storage cells and a set of conductors. The process steps that pattern the conductors also patterns the magnetic layers in the magnetic storage cells thereby avoiding the need to employ precise alignment between pattern masks.

Abstract: A circuit board for use in the production of semiconductor devices, in which the circuit board includes two or more by-pass capacitors formed thereon, and each by-pass capacitor is constituted from a first electrode layer formed in the uppermost layer of the circuit board, a ferroelectric layer formed, from a ferroelectric material having a higher dielectric constant than the upper electrode layer, over the first electrode layer, and a second electrode layer formed over the ferroelectric layer, and a semiconductor device comprising the circuit board having mounted thereon a semiconductor element. A circuit board-providing article for use in the production of the circuit board, and a process for the production of the circuit board and the semiconductor device, are also disclosed.

Abstract: A method of manufacturing a semiconductor device has the steps of: (a) forming a lower electrode made of rare metal above a semiconductor substrate; (b) depositing a capacitor dielectric film made of a high dielectric material or ferroelectric oxide on the lower electrode; (c) forming a laminated layer on the capacitor dielectric film, the laminated layer including an upper electrode layer made of rare metal and an adhesive layer with or without an SiO2 mask layer thereon; (d) patterning the laminated layer; (e) chemically processing the patterned, laminated layer to remove a surface layer of the laminated layer; and (f) forming an interlayer insulating film over the semiconductor substrate, covering the chemically processed, laminated layer. An adhesion force between the rare metal layer and insulating layer can be increased.

Abstract: The present invention utilizes a reducing plasma treatment step to enhance the adhesion of a subsequently deposited inorganic barrier film to a copper wire or via present in a semiconductor interconnect structure such as a dual damascene structure. Interconnect structure including a material layer of Cu, Si and O, as essential elements, is formed between said copper wire or via and the inorganic barrier film.

Abstract: A new method and processing sequence is provided for the formation of solder bumps that are in contact with underlying aluminum contact pads. A patterned layer of negative photoresist is interposed between a patterned layer of PE Si3N4 and a patterned layer of polyamide insulator. The patterned negative photoresist partially overlays the aluminum contact pad and prevents contact between the layer of polyamide insulator and the aluminum contact pad. By forming this barrier no moisture that is contained in the polyamide insulator can come in contact with the aluminum contact pad, therefore no corrosion in the surface of the aluminum contact pad can occur.

Abstract: The present invention discloses a method of increasing the contrast of an EUV mask at inspection by forming a multilayer mirror over a substrate; forming an absorber layer over the multilayer mirror; forming a top layer over the absorber layer; patterning the mask into a first region and a second region; and removing the top layer and the absorber layer in the first region.

Abstract: A method of manufacturing a semiconductor device which includes forming a first SiGe layer having a low content of Ge, forming an oxide layer by implanting oxygen ions into the first SiGe layer, and then annealing the first SiGe layer. The method also includes forming, on the first SiGe layer, a second SiGe layer which has a higher content of Ge than the first SiGe layer, forming a strained Si layer on the second SiGe layer, and forming a field effect transistor in which the strained Si layer is used a channel region. Further, a field effect transistor may be formed on a semiconductor substrate having an indefectible, high-quality, buried oxide layer and a largely strained Si layer, and hence a high-speed, low-power-consumption semiconductor device can be realized.

Abstract: A method for providing low power MOS devices that include resistive paths specifically designed to provide a specified resistance between the bulk material of the device and a well tie contact. By providing a resistive path, an equivalent RC circuit is introduced to the device that allows the bulk material potential to track the gate potential, thereby advantageously lowering the threshold voltage as the device turns on and raising the threshold voltage as the device turns off. In addition, the introduction of the resistive path also allows the bulk material potential to be controlled and stabilize at an equilibrium potential between switching events.

Abstract: The present invention relates to a method and system for non-thermal abatement of effluent species generated in a semiconductor processing unit. In the method, an effluent stream is introduced into a discharge reactor wherein the components of the effluent stream are subjected to a corona discharge and maintained therein for a sufficient time to detoxify and/or dissociate the harmful components of the effluent stream. The discharge reactor, maintained at approximately atmospheric pressure, is positioned after the low-pressure semiconductor processing chamber and connecting vacuum pump system to limit interference with the semiconductor plasma processing tool.

Abstract: An unlanded process for manufacturing semiconductor circuits. Optical proximity correction of the electrical connection region of a conductive line is carried out to increase the area so that alignment accuracy between the conductive line and a via/contact improves. Optical proximity correction of the photomask for forming a conductive line pattern is carried out by first determining the electrical connection regions in the conductive line pattern. The regions are expanded equi-directionally or extended outward direction along the edges of the conductive line to form magnified regions. Overlapping regions between the original conductive line pattern and the magnified regions, regions outside the conductive line pattern as well as regions too close to neighboring conductive line pattern are removed. The final magnified regions and the original conductive line pattern are combined to obtain an optical proximity corrected photomask.

Abstract: In accordance with the present invention, a method is provided for shrinking critical dimension in semiconductor processes. This method comprises a step of performing an over-exposure process to a photosensitive layer to form a patterned photosensitive layer on a substrate by using a patterned reticle. Due to the unexposed region of the photosensitive layer being diminished by over-exposure the critical dimension is shrunk. Then, a sacrificial layer is applied for the purpose of pattern reverse-transferring. Next, the patterned photosensitive layer is removed such that the pattern is transferred to the sacrificial layer with a shrunk critical dimension. In cooperation of the present exposure technology with the present invention, the shrinkage of a critical dimension is accomplished, for example, using an I-line exposure light source in a critical dimension of 0.25 &mgr;m process, or using a deep UV (ultraviolet) exposure light source in a critical dimension of 0.13 &mgr;m process.

Abstract: A process for producing a multiplicity of semiconductor wafers, which includes the following individual steps: (a) simultaneous polishing a front side and a back side of each semiconductor wafer between rotating polishing plates with a polishing fluid being supplied, the semiconductor wafer in each case resting in a cutout in a carrier and being kept on a specific geometric path, and all semiconductor wafers having a thickness t1 following the polishing; (b) assessment of each semiconductor wafer with regard to quality features which are stipulated for further processing; (c) further simultaneous polishing a front side and a back side of each of those semiconductor wafers which, according to quality inspection (b), do not satisfy the stipulated quality features, these semiconductor wafers having a thickness t2 following the further polishing; and (d) further assessment of each of those semiconductor wafers which were fed to step (c) with regard to quality features stipulated for further processing.

Abstract: The method for fabricating a capacitor forms a lower electrode of a capacitor over a substrate, adds impurity ions to upper portions of the lateral surfaces; and forms HSG-Si on surfaces of the lower electrode except the upper portions of the lateral surfaces.

Abstract: Methods for expanding trenches are disclosed. A trench is formed in a substrate having side walls including at least two crystallographic planes. One crystallographic plane is etchable at a faster rate than a second crystallographic plane. A dielectric layer is selectively grown on surfaces of the crystallographic planes such that the dielectric layer includes a greater thickness on one of the crystallographic plane than on the other. The dielectric layer and the substrate are etched such that an etch rate inversion is achieved. That is, the second crystallographic plane is effectively etched at a faster rate than the first crystallographic plane.

Abstract: A method for determining device yield of a semiconductor device design, includes determining statistics of at least one MOSFET parameter from a gate pattern, and calculating device yield from the at least one MOSFET parameter. The method provides a direct simulation link from device layout to device performance.

Abstract: A nitride hard mask (230) is used to isolate active areas of a DRAM cell. The shallow trench isolation (STI) method includes forming memory cells comprising deep trenches (216) on a semiconductor wafer (200). The memory cell deep trenches (216) are separated from active areas (212) by a region of substrate (212). A nitride hard mask (230) is formed over the semiconductor wafer (200). The wafer (200) is patterned with the nitride hard mask (230), and the wafer (200) is etched to remove the region of substrate (212) between the deep trenches and active areas to provide shallow trench isolation. An etch chemistry selective to the nitride hard mask (230) is used.