Patents Examined by Paresh Paghadal
  • Patent number: 10050356
    Abstract: An electrical arrangement (10), including: a first conductor (12) having a first generally planar contact area (34); a second conductor (12) having a second generally planar contact area (40); an intermediate conductor (44) having a first faying area (84) overlying the first contact area and a second faying area (86) overlying the second contact area; a compression arrangement configured to compress the first faying area and the first contact area toward each other and to compress the second faying area and the second contact area toward each other; and a dimpling structure (46) effective to create plural contact points (74) between the first faying area and the first contact area and between the second faying area and the second contact area when the first and the second faying areas and the first and second contact areas are compressed toward each other by the compression arrangement.
    Type: Grant
    Filed: December 19, 2014
    Date of Patent: August 14, 2018
    Assignee: SIEMENS ENERGY, INC.
    Inventor: Joshua S. McConkey
  • Patent number: 10038267
    Abstract: A circuit interconnect generally comprises an electrical connection pad, a shape memory material, and a flowable conductor. The electrical connection pad has an upper surface, a portion of which is covered by the shape memory material. The flowable conductor extends through the shape memory material and is electrically coupled to the electrical connection pad. The shape memory material has a first configuration at a first temperature and a second configuration at a second temperature. In the instance of the second temperature being greater than the first, the shape memory material has a first configuration that is substantially planar and a second configuration that is cupped.
    Type: Grant
    Filed: June 12, 2014
    Date of Patent: July 31, 2018
    Assignee: Palo Alto Research Center Incorporated
    Inventor: Scott J. Limb
  • Patent number: 10028393
    Abstract: A wiring substrate includes a core layer, a first wiring layer, a first insulating layer, a first via wiring, a second wiring layer, a second insulating layer, a second via wiring, a third wiring layer, a third insulating layer, a third via wiring, and a through-wiring. The through-wiring includes upper and lower end surfaces. The upper end surface has an area that is smaller than an area of the lower end surface. The upper surface of the first insulating layer is more flat than the lower surface of the third insulating layer. The second wiring layer has a wiring density that is higher than a wiring density of the first wiring layer.
    Type: Grant
    Filed: July 2, 2015
    Date of Patent: July 17, 2018
    Assignee: SHINKO ELECTRIC INDUSTRIES CO., LTD.
    Inventors: Noriyoshi Shimizu, Yusuke Gozu, Akio Rokugawa
  • Patent number: 9991689
    Abstract: A mounting assembly is for a power pedestal including a number of electrical components. The mounting assembly includes a plurality of mounting members including a first mounting member and a second mounting member each structured to engage an elongated support member and be coupled to the elongated support member. The elongated support member has an end portion. The plurality of mounting members are cooperatively structured to enclose the end portion.
    Type: Grant
    Filed: December 16, 2015
    Date of Patent: June 5, 2018
    Assignee: EATON INTELLIGENT POWER LIMITED
    Inventors: Chris Emmons Drueke, Jeffery Scott Kuykendall, Paul David Seff
  • Patent number: 9991027
    Abstract: An electric wire includes a conductor having a cross-sectional area of not less than 225 mm2 and not more than 275 mm2, an insulation provided so as to cover the outer periphery of the conductor, and a wire sheath provided so as to cover the outer periphery of the insulation. The amount of deflection is not less than 130 mm when, at 23° C., one end of the electric wire is fixed to a fixture table so that another end horizontally protrudes 400 mm from the fixture table and a weight of 2 kg is attached to the other end, and cracks and breaks do not occur when wound with a bending diameter of three times the diameter at ?40° C.
    Type: Grant
    Filed: November 9, 2015
    Date of Patent: June 5, 2018
    Assignee: Hitachi Metals, Ltd.
    Inventors: Tamotsu Kibe, Hisao Furuichi, Hiroshi Okikawa, Ryutaro Kikuchi
  • Patent number: 9984792
    Abstract: An electric wire includes a conductor having a cross-sectional area of not less than 290 mm2 and not more than 360 mm2, an insulation provided so as to cover the outer periphery of the conductor, and a wire sheath provided so as to cover the outer periphery of the insulation. The amount of deflection is not less than 120 mm when, at 23° C., one end of the electric wire is fixed to a fixture table so that another end horizontally protrudes 400 mm from the fixture table and a weight of 2 kg is attached to the other end, and cracks and breaks do not occur when wound with a bending diameter of three times the diameter at ?40° C.
    Type: Grant
    Filed: November 9, 2015
    Date of Patent: May 29, 2018
    Assignee: Hitachi Metals, Ltd.
    Inventors: Tamotsu Kibe, Hisao Furuichi, Hiroshi Okikawa, Ryutaro Kikuchi
  • Patent number: 9986656
    Abstract: A multi-receptacle housing assembly that includes a clamping assembly and a cover. The clamping assembly defines a first clamping section, a second clamping section and a cover support section. The first clamping section is located along a first side of the clamping assembly and is configured to clamp to a projection of an electronic device housing. The second clamping section is located along a second side of the clamping assembly opposite the first side and is configured to receive and support a plurality of electric receptacles. The cover removably is connected to the cover support section of the clamping assembly at least partially covering the first clamping section and the cover support section. The cover defines an opening dimensioned to expose at least a portion of the second clamping section and the plurality of electric receptacles.
    Type: Grant
    Filed: December 17, 2015
    Date of Patent: May 29, 2018
    Assignee: Nissan North America, Inc.
    Inventor: Lynn E Jarvenpaa
  • Patent number: 9978514
    Abstract: There is provided a multilayer ceramic electronic component including, a ceramic body including a plurality of dielectric layers stacked in a thickness direction, satisfying T/W>1.0 when a width and a thickness thereof are defined as W and T, respectively, and having a groove portion inwardly recessed in a length direction in at least one main surface thereof, a plurality of first and second internal electrodes disposed in the ceramic body to face each other, having the dielectric layers interposed therebetween, and alternately exposed through both end surfaces of the ceramic body, and first and second external electrodes formed to extend from the both end surfaces of the ceramic body to the at least one main surface having the groove portion formed therein.
    Type: Grant
    Filed: November 14, 2013
    Date of Patent: May 22, 2018
    Assignee: SAMSUNG ELECTRO-MECHANICS CO., LTD.
    Inventors: Byung Woo Han, Dae Bok Oh, Jae Yeol Choi, Sang Huk Kim
  • Patent number: 9955576
    Abstract: Provided is a touch panel. The touch panel includes a substrate and an electrode member disposed on the substrate. The electrode member includes a base material for electrode having first and second surfaces opposite to each other, a first electrode disposed on the first surface, and a second electrode disposed on the second surface.
    Type: Grant
    Filed: December 20, 2011
    Date of Patent: April 24, 2018
    Assignee: LG INNOTEK CO., LTD.
    Inventors: Dong Youl Lee, Young Jin Noh, Young Sun You, Sun Young Lee, Yong Jin Lee, Kyoung Hoon Chai
  • Patent number: 9934885
    Abstract: A gas turbine engine 10 is provided with electrical harness rafts 200 comprising electrical conductors embedded in a rigid composite material. The rafts 200 are used to transport electrical signals (which may be, for example power and/or control signals) around a gas turbine engine. Rafts 200 may be connected together and to other components using flexible cables, that may help to accommodate relative movement of the rafts 200, for example through vibration. The rafts 200 are lighter, more compact, and more convenient to handle than conventional electrical harnesses. The rafts 200 may provide a convenient and secure mounting surface for other components/systems of a gas turbine engine, such as EECs and/or fluid pipes.
    Type: Grant
    Filed: December 17, 2012
    Date of Patent: April 3, 2018
    Assignee: ROLLS-ROYCE plc
    Inventors: Paul Broughton, Robin Charles Kennea
  • Patent number: 9928935
    Abstract: A system and a method are presented. The system includes an electrically conducting material and an electrical insulation system. The electrical insulation system includes a layered insulation tape that has a first layer and a second layer. The first layer includes a mica paper and a binder resin in a range from about 5 wt % to about 12 wt % of the insulation tape. The second layer includes a composite of layered nanoparticles dispersed in a polyetheretherketone (PEEK) matrix. The second layer laminates the first layer. The method includes attaching the first layer and the second layer with or without the addition of further resin; using the layered insulation tape as a turn insulation and ground wall insulation for an electrically conducting material; and impregnating the system with a nanofiller-incorporated resin by a vacuum pressure impregnation method, to form an insulation system within the system.
    Type: Grant
    Filed: May 31, 2013
    Date of Patent: March 27, 2018
    Assignee: GENERAL ELECTRIC COMPANY
    Inventors: Weijun Yin, Lili Zhang, Lionel Durantay, Jean François Grignard
  • Patent number: 9922753
    Abstract: A cable may include a plurality of twisted pairs of individually insulated conductors and a separator positioned between the twisted pairs. The separator may include a longitudinally extending spine positioned between the plurality of twisted pairs, and a plurality of bristles may radially extend from the spine. A first portion of the bristles may extend between one or more sets of adjacent twisted pairs, and a second portion of the bristles may be compressed towards the spine by one or more of the plurality of twisted pairs. Additionally, a jacket may be formed around the twisted pairs and the separator.
    Type: Grant
    Filed: December 7, 2016
    Date of Patent: March 20, 2018
    Assignee: Superior Essex International LP
    Inventor: Thomas Christopher Cook
  • Patent number: 9907189
    Abstract: A multi-layer wiring board is configured having stacked therein, in a stacking direction, via an adhesive layer, a plurality of printed wiring bases in each of which a wiring pattern and a via are formed on/in a resin base. A multi-layer wiring board includes a movable portion configured from an elastic member and a void portion, the movable portion being formed in the printed wiring bases and adhesive layer in a periphery of a matrix-shaped plurality of multi-layer wiring portions disposed at a certain interval as viewed in a planar manner, and the movable portion joining the plurality of multi-layer wiring portions such that each of the multi-layer wiring portions is displaceable in the stacking direction and a direction of surfaces of the printed wiring bases.
    Type: Grant
    Filed: April 21, 2014
    Date of Patent: February 27, 2018
    Assignee: FUJIKURA LTD.
    Inventor: Nobuki Ueta
  • Patent number: 9875957
    Abstract: A wiring substrate includes a first wiring structure and a second wiring structure. The first wiring structure includes a first insulating layer, which covers a first wiring layer, and a via wiring. A first through hole of the first insulating layer is filled with the via wiring. The second wiring structure includes a second wiring layer and a second insulating layer. The second wiring layer is formed on an upper surface of the first insulating layer and an upper end surface of the via wiring. The second wiring layer partially includes a roughened surface. The second insulating layer is stacked on the upper surface of the first insulating layer and covers the second wiring layer. The second wiring structure has a higher wiring density than the first wiring structure. The roughened surface of the second wiring layer has a smaller surface roughness than the first wiring layer.
    Type: Grant
    Filed: July 6, 2015
    Date of Patent: January 23, 2018
    Assignee: Shinko Electric Industries Co., Ltd.
    Inventors: Noriyoshi Shimizu, Yusuke Gozu, Jun Furuichi, Akio Rokugawa, Takashi Ito
  • Patent number: 9870969
    Abstract: The present invention relates to a substrate comprising a build-up and a solder resist layer disposed on the build-up. The solder resist layer has an upper surface facing away from the build-up. The solder resist layer has a plurality of grooves on its upper surface. The grooves of the solder resist layer can better eliminate or relieve the stress accumulated on large solder resist area induced by heat and/or material coefficient of thermal expansion mismatch of the substrate and thus can prevent and diminish warpage of the substrate or package.
    Type: Grant
    Filed: February 28, 2014
    Date of Patent: January 16, 2018
    Assignee: ADVANCED MICRO DEVICES (SHANGHAI) CO., LTD.
    Inventors: I-Tseng Lee, Yu-Ling Hsieh
  • Patent number: 9859201
    Abstract: A wiring substrate includes a first wiring structure and a second wiring structure stacked thereon. The first wiring structure includes a first insulation layer and a via wiring extending through the first insulation layer. The second wiring structure includes a first wiring layer formed on the first insulation layer and the via wiring, and a first plane layer stacked on the first insulation layer and at least partially grid-shaped in a plan view to define second through holes. A second insulation layer is stacked on the first insulation layer to fill the second through holes and cover the first plane layer and the first wiring layer. The second wiring structure has a higher wiring density than the first wiring structure. The second through holes each include a lower open end and an upper open end having a smaller open width than the lower open end.
    Type: Grant
    Filed: June 4, 2015
    Date of Patent: January 2, 2018
    Assignee: Shinko Electric Industries Co., Ltd.
    Inventors: Noriyoshi Shimizu, Kiyoshi Oi, Yuichiro Shimizu
  • Patent number: 9860985
    Abstract: A system and method of isolating a layer-to-layer transition between conductors in a multilayer printed circuit board includes formation of a first ground via at least partially surrounding a first signal conductor in at least one layer of the printed circuit board and formation of a second ground via at least partially surrounding a second signal conductor in another layer of the printed circuit board. The first and second ground vias are plated with a conductive material.
    Type: Grant
    Filed: December 17, 2012
    Date of Patent: January 2, 2018
    Assignee: Lockheed Martin Corporation
    Inventor: Jack V. Ajoian
  • Patent number: 9847154
    Abstract: Communication cable including insulated conductors and a composite tape having an insulative layer and a conductive layer. The composite tape includes first and second lateral sections that are folded over each other to form a shielding tape. The shielding tape includes opposite inner and outer sides that are formed from the first and second lateral sections, respectively, and a folded edge that joins the inner and outer sides. The conductive layer defines the inner side, the outer side, and the folded edge. The shielding tape is wrapped helically about the insulated conductors a plurality of times along a length of the communication cable to form a plurality of wraps. The inner side of a subsequent wrap of the shielding tape overlaps a portion of the outer side of a prior wrap of the shielding tape.
    Type: Grant
    Filed: October 27, 2014
    Date of Patent: December 19, 2017
    Assignee: TE CONNECTIVITY CORPORATION
    Inventors: Charles Lloyd Grant, Andrew John Nowak, Thomas Joseph Grzysiewicz, Paul Leo Grant, Roger Edward Temple, Victor William Lee, Rama Krishna Nippani
  • Patent number: 9826646
    Abstract: A component built-in board comprises a multi-layer structure comprising a plurality of unit boards stacked therein a plurality of electronic components built in thereto in a stacking direction. The plurality of unit boards include: a first board having a first insulating layer and comprising an opening in which the electronic component is housed; and an intermediate board adjacent to the first board and comprising a first adhesive layer provided on at least a side of the first board of a second insulating layer. The intermediate board includes a first wiring layer formed at a position overlapping in the stacking direction a gap between an inner periphery of the opening and an outer periphery of the electronic component of the first board on a surface on the first board side of the second insulating layer.
    Type: Grant
    Filed: May 26, 2015
    Date of Patent: November 21, 2017
    Assignee: FUJIKURA LTD.
    Inventor: Koji Munakata
  • Patent number: 9820391
    Abstract: A wiring board includes first insulating layers; first wiring layers; first via wirings; second insulating layers; second wiring layers; second via wirings; and a solder resist layer, wherein the first insulating layers are composed of non-photosensitive resin, wherein the second insulating layers, and the solder resist layer are composed of photosensitive resin, respectively, wherein the first surface of the uppermost first insulating layer and the first end surface of the first via wiring embedded in the uppermost first insulating layer are polished surfaces, wherein the first end surface of the first via wiring embedded in the uppermost first insulating layer is flush with the first surface of the uppermost first insulating layer, and wherein the wiring density of the second wiring layers is higher than the wiring density of the first wiring layers.
    Type: Grant
    Filed: February 4, 2015
    Date of Patent: November 14, 2017
    Assignee: SHINKO ELECTRIC INDUSTRIES CO., LTD.
    Inventors: Noriyoshi Shimizu, Shoji Watanabe, Toshinori Koyama, Akio Rokugawa