Abstract: Aspects of the present disclosure include fabricating integrated circuit (IC) structures using a boron etch-stop layer, and IC structures with a boron-rich region therein. Methods of forming an IC structure according to the present disclosure can include: growing a conductive epitaxial layer on an upper surface of a semiconductor element; forming a boron etch-stop layer directly on an upper surface of the conductive epitaxial layer; forming an insulator on the boron etch-stop layer; forming an opening within the insulator to expose an upper surface of the boron etch-stop layer; annealing the boron etch-stop layer to drive boron into the conductive epitaxial layer, such that the boron etch-stop layer becomes a boron-rich region; and forming a contact to the boron-rich region within the opening, such that the contact is electrically connected to the semiconductor element through at least the conductive epitaxial layer.

Abstract: Embodiments of the invention disclose an array substrate and a fabrication method thereof, and a display device. The array substrate comprises a plurality of pixel units disposed on a base substrate, and the pixel unit comprises a thin-film transistor structure region and a display region other than the thin-film transistor structure region. A thin-film transistor structure is formed in the thin-film transistor structure region, an organic light-emitting diode is formed in the display region, and the thin-film transistor structure is configured to drive the organic light-emitting diode. A light-shielding layer is formed above the thin-film transistor structure in the thin-film transistor structure region, and the light-shielding layer is configured to block a blue light from entering the thin-film transistor structure.

Abstract: Embodiments are directed to a package that includes an electric device having a recess. In one embodiment, the electric device is a sensor and the recess reduces signal drift of the sensor caused by thermal expansion of the package. In another embodiment, the recess is substantially filled with adhesive material, thus increasing adhesion between the electric device and a substrate of the package while at the same time allowing for lower adhesive fillets.

Abstract: Semiconductor devices and methods for manufacturing the same are provided. In one embodiment, the method may include: forming a first shielding layer on a substrate, and forming one of source and drain regions with the first shielding layer as a mask; forming a second shielding layer on the substrate, and forming the other of the source and drain regions with the second shielding layer as a mask; removing a portion of the second shielding layer which is next to the other of the source and drain regions; forming a gate dielectric layer, and forming a gate conductor as a spacer on a sidewall of a remaining portion of the second shielding layer; and forming a stressed interlayer dielectric layer on the substrate.

Abstract: Embodiments of the invention include a semiconductor light emitting device, a first wavelength converting member disposed on a top surface of the semiconductor light emitting device, and a second wavelength converting member disposed on a side surface of the semiconductor light emitting device. The first and second wavelength converting members include different wavelength converting materials.

Abstract: A curable composition including: (A) an ester bond-containing organosilicon compound having two or more addition reactive carbon-carbon double bonds in one molecule, shown by the following general formula (1); (B) a silicon compound having two or more silicon atom-bonded hydrogen atoms in one molecule; and (C) a hydrosilylation reaction catalyst. This provides a curable composition to give a cured product with low gas permeability as well as excellent crack resistance and light transmission property.

Abstract: A tandem organic light emitting diode and a preparation method thereof are provided. The tandem organic light emitting diode includes: at least two light-emitting units (11, 12); a charge generation layer (21) disposed between the light emitting units (11, 12); wherein, the charge generation layer (21) includes a mixed conductive layer (211), and the mixed conductive layer (211) is made by mixing at least one material having a conductivity greater than 103 S/cm with a content of 5˜95 wt % and at least one material having a conductivity less than 10?6 S/cm with a content of 95˜5 wt %. The tandem organic light emitting diode is applicable in a display device.

Abstract: A power cell includes a fin over a substrate, the fin extending in a direction substantially perpendicular to a bottom surface of the substrate. The fin includes a first dopant type. The power cell further includes at least one isolation region over the substrate between the fin and an adjacent fin. The power cell further includes a gate structure in contact with the fin and the at least one isolation region, wherein the gate structure comprises a doped region in the fin, wherein the doped region has a second dopant type different from the first dopant type and the doped region defines a channel region in the fin.

Abstract: A device comprises a top package mounted on a bottom package, wherein the bottom package comprises a plurality of interconnection components and the bottom package comprises a plurality of first bumps formed on a first side of the bottom package, a semiconductor die is bonded on a second side of the bottom package, wherein the semiconductor die is electrically coupled to the first bumps through the interconnection components and the semiconductor die is located between the top package and the bottom package, and an underfill layer formed between the top package and the bottom package.

Abstract: A method and structure for forming an array of LED devices is disclosed. The LED devices in accordance with embodiments of the invention may include a confined current injection area, embedded mirror, or sidewall passivation layer, and any combination thereof.

Abstract: Embodiments of the present disclosure describe techniques and configurations to reduce transistor gate short defects. In one embodiment, a method includes forming a plurality of lines, wherein individual lines of the plurality of lines comprise a gate electrode material, depositing an electrically insulative material to fill regions between the individual lines and subsequent to depositing the electrically insulative material, removing a portion of at least one of the individual lines to isolate gate electrode material of a first transistor device from gate electrode material of a second transistor device. Other embodiments may be described and/or claimed.

Abstract: To provide an imaging device equipped with a photodiode, which is capable of enhancing both of a capacity and sensitivity. In an area of a P-type well in which a photodiode is formed, a P-type impurity region is formed from the surface of the P-type well to a predetermined depth. Further, an N-type impurity region is formed to extend to a deeper position. N-type impurity regions and P-type impurity regions respectively extending in a gate width direction from a lower part of the N-type impurity region to a deeper position so as to contact the N-type impurity region are alternately arranged in a plural form along a gate length direction in a form to contact each other.

Abstract: A method of forming a semiconductor device includes following steps. Firstly, a substrate having a transistor is provided, where the transistor includes a source/drain region. A dielectric layer is formed on the substrate, and a contact plug is formed in the dielectric layer to electrically connect the source/drain region. Next, a mask layer is formed on the dielectric layer, where the mask layer includes a first layer and a second layer stacked thereon. After this a slot-cut pattern is formed on the second layer of the mask layer, and a contact slot pattern is formed on the first layer of the mask layer. Finally, the second layer is removed and a contact opening is formed by using the contact slot pattern on the first layer.

Abstract: Radiation detectors are disclosed. The radiation detectors comprise a substrate and at least one radiation sensitive region on the substrate, the at least one radiation sensitive region comprising an array of elongate nanostructures projecting from the substrate. Methods of manufacture of such radiation detectors are also disclosed.

Abstract: The present disclosure provides a lighting device comprising: a reflective element layer; an optical resin layer formed on the reflective element layer; a transparent electrode film layer formed on the optical resin layer; and a plurality of light-emitting units formed on the lower surface of the transparent electrode film layer. The lighting device allows the fundamental cause of the hot spot phenomenon to be eliminated, shows excellent luminous efficiency by efficiently performing the function of a surface light source, and enables the kinds of raw materials and the number of production processes to be reduced by eliminating the use of a PCB board and selectively applying second reflective patterns.

Abstract: In a fabrication method of a silicon carbide semiconductor element including a drift layer playing a role of retaining a high withstand voltage on a front side of a semiconductor substrate of silicon carbide and including an ohmic electrode on a backside, dicing is added to form at least one dicing line in an element active region on a surface of the semiconductor substrate on a side opposite of the drift layer before forming the ohmic electrode on the backside of the semiconductor substrate. Thus, a silicon carbide semiconductor element and fabrication method thereof is provided such that even if the semiconductor substrate is made thinner to reduce the on-resistance, the strength of the substrate can be maintained and cracking of the wafer during wafer processing can be reduced.

Abstract: A step-flow growth of a group-III nitride single crystal on a silicon single crystal substrate is promoted. A layer of oxide oriented to a <111> axis of silicon single crystal is formed on a surface of a silicon single crystal substrate, and group-III nitride single crystal is crystallized on a surface of the layer of oxide. Thereupon, a <0001> axis of the group-III nitride single crystal undergoing crystal growth is oriented to a c-axis of the oxide. When the silicon single crystal substrate is provided with a miscut angle, step-flow growth of the group-III nitride single crystal occurs. By deoxidizing a silicon oxide layer formed at an interface of the silicon single crystal and the oxide, orientation of the oxide is improved.

Abstract: A semiconductor structure includes a first fin structure, a gate structure, a first spacer, and a second space spacer. The gate structure traverses the first fin structure. The first fin structure has an exposed portion exposed out of the gate structure. The first spacer is positioned at and in contact with a side of the exposed portion of the first fin structure. The second space spacer is positioned at and in contact with another side of the exposed portion of the first fin structure. The first spacer has a top surface over than a top surface of the second spacer.

Abstract: A method of forming an on-chip heat sink includes forming a device on a substrate. The method also includes forming a plurality of insulator layers over the device. The method further includes forming a heat sink in at least one of the plurality of insulator layers and proximate to the device. The heat sink includes a reservoir of phase change material having a melting point temperature that is less than an upper limit of a design operating temperature of the chip.

Abstract: A semiconductor device including an insulating film in a first region of a semiconductor substrate; a first impurity region and a second impurity region of a first conductivity type, each of the regions including a part located deeper than the insulating film in contact with each other, and the insulating film being sandwiched by the first and second impurity regions in planar view in the first region of the semiconductor substrate; a metal silicide film on the first impurity region and in Schottky junction with the first impurity region; a first impurity of the first impurity region having a peak of a concentration profile deeper than a bottom of the insulating film; a second impurity of the second impurity region having a concentration higher than a concentration of the first impurity in a part of the first impurity region shallower than the bottom of the insulating film.