Abstract: Methods and apparatus are provided for an integrated circuit with a transistor and a resistor. The method includes depositing a first dielectric layer over the transistor and the resistor, followed by an amorphous silicon layer. The amorphous silicon layer is implanted over the resistor to produce an etch mask, and the amorphous silicon layer and first dielectric layer are removed over the transistor. A contact location on the transistor is then silicided.

Abstract: An ultrasonic transducer and a method of manufacturing the same are disclosed. The ultrasonic transducer includes a first electrode layer which is disposed to cover a conductive substrate and an inner wall and a top of a via hole penetrating a membrane and has a top surface at a same height as a top surface of the membrane; a second electrode layer which is disposed on a bottom surface of the conductive substrate to be spaced apart from the first electrode layer; and a top electrode which is disposed on the top surface of the membrane and which contacts the top surface of the first electrode layer.

Abstract: A method of forming an on-chip heat sink includes forming a device on a substrate. The method also includes forming a plurality of insulator layers over the device. The method further includes forming a heat sink in at least one of the plurality of insulator layers and proximate to the device. The heat sink includes a reservoir of phase change material having a melting point temperature that is less than an upper limit of a design operating temperature of the chip.

Abstract: A method of forming an on-chip heat sink includes forming a device on a substrate. The method also includes forming a plurality of insulator layers over the device. The method further includes forming a heat sink in at least one of the plurality of insulator layers and proximate to the device. The heat sink includes a reservoir of phase change material having a melting point temperature that is less than an upper limit of a design operating temperature of the chip.

Abstract: An organic light emitting diode display includes a substrate, a planarization layer disposed on the substrate, a first electrode disposed on the planarization layer, an emission layer disposed on the first electrode, and a second electrode disposed on the emission layer, wherein an uneven pattern is formed on a top surface of the planarization layer, the uneven pattern comprises a strip line having a plurality of thicknesses and widths, and a thickness of the strip line becomes smaller as a distance from a center portion of the first electrode becomes larger.

Abstract: Disclosed are a light emitting device, a method of manufacturing the same, a light emitting device package, and a lighting system. The light emitting device includes: a substrate; a first conductive semiconductor layer on the substrate; an active layer on the first conductive semiconductor layer; a second conductive semiconductor layer; and a nitride semiconductor layer having a refractive index less than a refractive index of the second conductive semiconductor layer on the second conductive semiconductor layer.

Abstract: A thin film transistor array panel is disclosed. The thin film transistor array panel may include a gate line disposed on a substrate and including a gate electrode, a semiconductor layer including an oxide semiconductor disposed on the substrate, a data wiring layer disposed on the substrate and including a data line crossing the gate line, a source electrode connected to the data line and a drain electrode facing the source electrode, a polymer layer covering the source electrode and the drain electrode, and a passivation layer disposed on the polymer layer. The data wiring layer may include copper or a copper alloy and the polymer layer may include fluorocarbon.

Abstract: A light-emitting element includes a reflective electrode, a light-transmitting electrode disposed opposite the reflective electrode, a light-emitting layer emitting blue light disposed between the reflective electrode and the light-transmitting electrode, and a functional layer disposed between the reflective electrode and the light-emitting layer. The optical thickness of the functional layer is no less than 428.9 nm and no more than 449.3 nm.

Abstract: A semiconductor device including a nonvolatile memory cell with a high performance and also a high reliability is provided. A nonvolatile memory cell includes a first n-well, a second n-well separated from the first n-well in a first direction, a selection transistor formed in the first n-well, a floating gate electrode formed to overlap with a part of the first n-well and a part of the second n-well in a plan view, and an n-conductivity-type semiconductor regions formed in the second n-well on both sides of the floating gate electrode. In write operation, ?7 V is applied to the drain of a selected nonvolatile memory cell, ?8 V is applied to the gate electrode of the selection transistor, and further ?3 V is applied to the n-conductivity-type semiconductor region for obtaining a higher write speed. Thereby, a selected nonvolatile memory cell is discriminated from an unselected nonvolatile memory cell.

Abstract: A field effect transistor includes an active layer and a capping layer sequentially stacked on a substrate, and a gate electrode penetrating the capping layer and being adjacent to the active layer. The gate electrode includes a foot portion adjacent to the active layer and a head portion having a width greater than a width of the foot portion. The foot portion of an end part of the gate electrode has a width less than a width of the head portion of another part of the gate electrode and greater than a width of the foot portion of the another part of the gate electrode. The foot portion of the end part of the gate electrode further penetrates the active layer so as to be adjacent to the substrate.

Abstract: According to one embodiment, a semiconductor device has a first nitride semiconductor layer, a second nitride semiconductor layer provided on the first nitride semiconductor layer and formed of a non-doped or n-type nitride semiconductor having a band gap wider than that of the first nitride semiconductor layer, a heterojunction field effect transistor having a source electrode, a drain electrode, and a gate electrode, a Schottky barrier diode having an anode electrode and a cathode electrode, and first and second element isolation insulating layers. The first element isolation insulating layer has a first end contacting with the drain electrode and the anode electrode, and a second end located in the first nitride semiconductor layer. The second element isolation insulating layer has a third end contacting with the cathode electrode, and a fourth end located in the first nitride semiconductor layer.

Abstract: A semiconductor package includes a circuit board having an inner circuit pattern and a plurality of contact pads connected to the inner circuit pattern, at least one integrated circuit (IC) device on the circuit board and making contact with the contact pads, a mold on the circuit board, the mold fixing the IC device to the circuit board, and a surface profile modifier on a surface of the IC device and a surface of the mold, and the surface profile modifier enlarging a surface area of the IC device and the mold to dissipate heat.

Abstract: A method and apparatus for enhancing the thermal performance of semiconductor packages effectively. The concept of this invention is to provide silicon nanowires on the backside of an integrated circuit die to directly attach the die to the substrate, thereby improving the interface between die and substrate, and thus enhancing thermal performance and enhancing reliability by improving adhesion.

Abstract: A vertical thin-film transistor structure includes a substrate, a source electrode, an insulation layer, a drain electrode, two first channel layers, a gate insulation layer and a gate electrode, which are stacked upward in that order on the substrate. The first channel layers are respectively disposed at two opposite ends of the drain electrode, and extend from the upper surface of the drain electrode to the upper surface of the source electrode respectively. Each of the first channel layers contacts the source electrode and the drain electrode. The gate insulation layer is disposed on the source electrode, the first channel layers and the drain electrode. The gate electrode is disposed on the gate insulation layer and covers the first channel layers. Therefore, the volume of the conventional thin-film transistor structure shrinks, and the ratio of the volume of the conventional thin-film transistor structure to that of a pixel structure decreases.

Abstract: Making it possible to improve adhesion between the semiconductor layer and the electrodes, realize high-speed operation of the thin-film transistor by enhancing ohmic contact between these members, reliably prevent oxidation of the electrode surfaces, and realize an electrode fabrication process with few processing steps. The thin-film transistor 10 of the present invention includes a semiconductor layer 4 composed of oxide semiconductor, a source electrode 5 and a drain electrode 6 that are layers composed mainly of copper, and oxide reaction layers 22 provided between the semiconductor layer 4 and each of the source electrode 5 and drain electrode 6, and high-conductance layers 21 provided between the oxide reaction layers 22 and semiconductor layer 4.

Abstract: A semiconductor device includes a substrate having at least one electrically insulating portion. A first graphene electrode is formed on a surface of the substrate such that the electrically insulating portion is interposed between a bulk portion of the substrate and the first graphene electrode. A second graphene electrode formed on the surface of the substrate. The electrically insulating portion of the substrate is interposed between the bulk portion of the substrate and the second graphene electrode. The second graphene electrode is disposed opposite the first graphene electrode to define an exposed substrate area therebetween.

Abstract: A memory device may include a semiconductor substrate, and a memory transistor in the semiconductor substrate. The memory transistor may include source and drain regions in the semiconductor substrate and a channel region therebetween, and a gate stack having a first dielectric layer over the channel region, a second dielectric layer over the first dielectric layer, a first diffusion barrier layer over the second dielectric layer, a first electrically conductive layer over the first diffusion barrier layer, a second diffusion barrier layer over the first electrically conductive layer, and a second electrically conductive layer over the second diffusion barrier layer. The first and second dielectric layers may include different dielectric materials, and the first diffusion barrier layer may be thinner than the second diffusion barrier layer.

Abstract: A field effect nano-pillar transistor has a pillar shaped gate element incorporating a biomimitec portion that provides various advantages over prior art devices. The small size of the nano-pillar transistor allows for advantageous insertion into cellular membranes, and the biomimitec character of the gate element operates as an advantageous interface for sensing small amplitude voltages such as transmembrane cell potentials. The nano-pillar transistor can be used in various embodiments to stimulate cells, to measure cell response, or to perform a combination of both actions.

Abstract: The invention relates to an organic light emitting device having an electrode, a counter electrode, at least one light emitting region that includes a stack of organic layers between the electrode and the counter electrode, which stack of organic layers is provided between a metal substrate and a transparent encapsulation, a current supply layer, electrically connected to the electrode or the counter-electrode, the current supply layer being partially provided overlapping an electric insulating layer provided in direct contact with the metal substrate, and at least one electrical feedthrough through the metal substrate and through the electric insulating layer, which electrical feedthrough provides an electrical connection to the current supply layer and is electrically isolated from the metal substrate.

Abstract: Stacked multichip packages and methods of making multichip packages. A method includes using a boat having different depth openings corresponding to the length of column interconnections of the completed multichip package and masks to place proper length columns in the corresponding depth openings; placing an integrated circuit chip on the boat and attaching exposed upper ends of the columns to respective chip pads of the integrated circuit using a first solder reflow process and attaching a preformed package substrate integrated circuit chip stack to the integrated circuit and attached columns using a second solder reflow process.