Patents Examined by Patricia T. Nguyen
  • Patent number: 11519754
    Abstract: Isolated circuit systems are provided. The systems include a primary side circuit and a secondary circuit, electrically isolated from each other. The primary side and secondary side circuits each utilize a direct current (DC) reference signal. The primary side circuit may use the DC reference signal in a modulation operation. The secondary side circuit may use the DC reference signal in a demodulation operation. The DC reference signal may be sent from the primary side circuit to the secondary side circuit, or from the secondary side circuit to the primary side circuit.
    Type: Grant
    Filed: May 29, 2020
    Date of Patent: December 6, 2022
    Assignee: Analog Devices International Unlimited Company
    Inventors: Wenhui Qin, Shaoyu Ma, Tianting Zhao, Fang Liu
  • Patent number: 11515846
    Abstract: An in-band extraction unit is configured to extract an in-band from an output signal. An out-band extraction unit is configured to extract at least one pair of out-bands including a low frequency side out-band and a high frequency side out-band from the output signal. An ADC is configured to convert the extracted in-band and out-bands to digital signals. A signal processing unit is configured to process information included in the digital signals converted by the analog to digital converter and adjust an operation of predistorting an input baseband digital signal to generate the output signal.
    Type: Grant
    Filed: December 4, 2017
    Date of Patent: November 29, 2022
    Assignee: NEC CORPORATION
    Inventors: Soubhik Deb, Masaaki Tanio
  • Patent number: 11515847
    Abstract: A packaged RF amplifier device includes input and output leads and a transistor die. The transistor die includes a transistor with a drain-source capacitance below 0.1 picofarads per watt. The device also includes a conductive connection between the transistor output terminal and the output lead, and a baseband termination circuit between the transistor output terminal and a ground reference node. The baseband termination circuit presents a low impedance to signal energy at envelope frequencies and a high impedance to signal energy at RF frequencies. The baseband termination circuit includes an inductive element, a resistor, and a capacitor connected in series between the transistor output terminal and the ground reference node. Except for a minimal impedance transformation associated with the conductive connection, the device is unmatched between the transistor output terminal and the output lead by being devoid of impedance matching circuitry between the transistor output terminal and the output lead.
    Type: Grant
    Filed: September 16, 2020
    Date of Patent: November 29, 2022
    Assignee: NXP USA, Inc.
    Inventors: Damon G. Holmes, Ning Zhu, Jeffrey Spencer Roberts, Jeffrey Kevin Jones
  • Patent number: 11515845
    Abstract: Solder bumps are placed in direct contact with the silicon substrate of an amplifier integrated circuit having a flip chip configuration. A plurality of amplifier transistor arrays generate waste heat that promotes thermal run away of the amplifier if not directed out of the integrated circuit. The waste heat flows through the thermally conductive silicon substrate and out the solder bump to a heat-sinking plane of an interposer connected to the amplifier integrated circuit via the solder bumps.
    Type: Grant
    Filed: September 1, 2020
    Date of Patent: November 29, 2022
    Assignee: Skyworks Solutions, Inc.
    Inventors: Michael Joseph McPartlin, Bharatjeet Singh Gill, Stephen Joseph Kovacic
  • Patent number: 11509270
    Abstract: Systems, methods and apparatus for practical realization of an integrated circuit comprising a stack of transistors operating as an RF amplifier are described. As stack height is increased, capacitance values of gate capacitors used to provide a desired distribution of an RF voltage at the output of the amplifier across the stack may decrease to values approaching parasitic/stray capacitance values present in the integrated circuit which may render the practical realization of the integrated circuit difficult. Coupling of an RF gate voltage at the gate of one transistor of the stack to a gate of a different transistor of the stack can allow for an increase in the capacitance value of the gate capacitor of the different transistor for obtaining an RF voltage at the gate of the different transistor according to the desired distribution.
    Type: Grant
    Filed: November 24, 2020
    Date of Patent: November 22, 2022
    Assignee: pSemi Corporation
    Inventor: Jaroslaw Adamski
  • Patent number: 11502659
    Abstract: Disclosed herein is a voltage gain amplifier for use in an automotive radar receiver chain. The voltage gain amplifier utilizes pole-zero cancelation to yield a desired transfer function without gain peaking at a bandwidth in which attenuation is desired, and utilizes a low pass filter effectively formed by a feedback loop including a high pass filter and a differential amplifier to ensure the desired level of attenuation at the desired bandwidth. In some instances, a chopper may be utilized in the feedback loop prior to the high pass filter, and after the differential amplifier, so as to reduce the bandwidth of the differential amplifier in the feedback loop.
    Type: Grant
    Filed: June 17, 2020
    Date of Patent: November 15, 2022
    Assignee: STMicroelectronics International N.V.
    Inventor: Riju Biswas
  • Patent number: 11502651
    Abstract: An overvoltage protection and gain bootstrap circuit of a power amplifier includes a power amplification transistor, and a diode reversely connected with a gate of the power amplification transistor. A negative electrode of the diode is connected with the gate of the power transistor, and a positive electrode of the diode is connected with a constant voltage source, such that a function of overvoltage protection and gain bootstrap of the circuit is realized by controlling a turn-on state of the diode. By adding a diode device to the circuit, gate-drain overvoltage protection for the power amplification transistor can be provided, and the gain of the amplifier can be improved before power compression, thereby improving linearity of the power amplifier. The structure of the circuit can be simple, with reduced occupied area hardware cost.
    Type: Grant
    Filed: December 30, 2020
    Date of Patent: November 15, 2022
    Assignee: SMARTER MICROELECTRONICS (GUANG ZHOU) CO., LTD.
    Inventors: Zhenfei Peng, Qiang Su, Kun Xiang
  • Patent number: 11502658
    Abstract: The detection matrix for an Orthogonal Differential Vector Signaling code is typically embodied as a transistor circuit with multiple active signal inputs. An alternative detection matrix approach uses passive resistor networks to sum at least some of the input terms before active detection.
    Type: Grant
    Filed: February 23, 2021
    Date of Patent: November 15, 2022
    Assignee: KANDOU LABS, S.A.
    Inventors: Suhas Rattan, Kiarash Gharibdoust
  • Patent number: 11496105
    Abstract: A multi-stage amplifier circuit includes a pre-stage amplifier circuit and a floating control circuit. The pre-stage amplifier circuit amplifies a voltage difference between its input terminals, to generate plural pre-stage transconductance currents flowing through corresponding plural pre-stage transconductance nodes. The floating control circuit includes: a floating reference transistor configured as a source follower and a floating amplifier. The floating amplifier and the floating reference transistor are coupled to form feedback control and to generate an upper driving signal and a lower driving signal according to a floating reference level in the floating control circuit. The upper driving signal is higher than the lower driving signal with a predetermined voltage difference. The floating control circuit is electrically connected to the plural pre-stage transconductance nodes and is floating in common mode relative to the pre-stage transconductance nodes.
    Type: Grant
    Filed: October 1, 2021
    Date of Patent: November 8, 2022
    Assignee: RICHTEK TECHNOLOGY CORPORATION
    Inventor: Min-Hung Hu
  • Patent number: 11496100
    Abstract: A matching network is a matching network of a power amplifier circuit that outputs a signal obtained by a differential amplifier amplifying power of a high-frequency signal. The matching network includes an input-side winding connected between differential outputs of the differential amplifier; an output-side winding that is coupled to the input-side winding via an electromagnetic field and whose one end is connected to a reference potential; a first LC series resonant circuit including a capacitive element and an inductive element connected in series with each other, and being connected in parallel with the input-side winding; and a second LC series resonant circuit including a capacitive element and an inductive element connected in series with each other, and being connected in parallel with the output-side winding.
    Type: Grant
    Filed: September 3, 2020
    Date of Patent: November 8, 2022
    Assignee: MURATA MANUFACTURING CO., LTD.
    Inventors: Kiichiro Takenaka, Masahiro Ito, Tsuyoshi Sato, Kozo Sato, Hidetoshi Matsumoto
  • Patent number: 11489496
    Abstract: A circuit arrangement, including: a circuit configured to synthesize a resistor having a resistance value having a variation in time equivalent to a resistance variation of a sensor resistor applied with a resistance bias voltage and a resistance current bias, wherein the circuit includes: an amplifier comprising an input transistor; a bias current generator comprising a control node coupled to an output of the input transistor, wherein the bias current generator is configured to generate a bias current flowing in the input transistor; and a further current generator configured to generate a current at least proportional to the resistance bias current and coupled to the output of the input transistor, wherein the resistance bias voltage is applied to an input of the amplifier, and wherein a transconductance of the input transistor is at least proportional to the resistance of the sensor resistor.
    Type: Grant
    Filed: February 10, 2021
    Date of Patent: November 1, 2022
    Assignee: STMICROELECTRONICS S.R.L.
    Inventors: Mattia Fausto Moretti, Paolo Pulici, Alessio Facen
  • Patent number: 11489504
    Abstract: An integrated amplifier device includes a main amplifier configured to be coupled to an input source. A replica amplifier is coupled to the main amplifier to provide a bias to the main amplifier. A transconductance biasing cell to the main amplifier and the replica amplifier. The transconductance biasing cell is configured to bias both the main amplifier and the replica amplifier. A method of making an integrated amplifier device is also disclosed.
    Type: Grant
    Filed: April 9, 2020
    Date of Patent: November 1, 2022
    Assignee: INTRINSIX CORP.
    Inventor: Daniel J. Segarra
  • Patent number: 11489501
    Abstract: According to one aspect, embodiments of the invention provide a distortion detection circuit comprising an input configured to be coupled to an output stage of an amplifier and to receive an RF signal from the output stage of the amplifier, an output configured to be coupled to a module of the amplifier, at least one peak detection circuit coupled to the input and configured to monitor the RF signal and output a first signal based on positive voltage peaks of the RF signal, and a differential amplifier having an input coupled to the at least one peak detection circuit and configured to monitor the first signal and provide a second signal to the output in response to a voltage of the first signal exceeding a threshold level indicative of distortion in the RF signal.
    Type: Grant
    Filed: October 16, 2020
    Date of Patent: November 1, 2022
    Assignee: SKYWORKS SOLUTIONS, INC.
    Inventor: Gordon Glen Rabjohn
  • Patent number: 11482974
    Abstract: An RF power amplifier is described including a first amplifier and a second amplifier arranged in parallel between an RF power amplifier input and an RF power amplifier output. A phase adjuster adjusts the phase of a signal on at least one of the first amplifier signal path and the second amplifier signal path. A first impedance inverter has a first impedance inverter input coupled to an output of the second amplifier and a first impedance inverter output coupled to the RF power amplifier output. The RF power amplifier is configured to enable at least one of the first amplifier and the second amplifier dependent on an operation mode and the first impedance inverter is configured to modulate the load impedance of the second amplifier in response to the operation mode changing.
    Type: Grant
    Filed: September 22, 2020
    Date of Patent: October 25, 2022
    Assignee: NXP B.V.
    Inventors: Gerben Willem de Jong, Mark Pieter van der Heijden, Jozef Reinerus Maria Bergervoet
  • Patent number: 11476815
    Abstract: Envelope tracking systems for power amplifiers are provided herein. In certain embodiments, an envelope tracker is provided for a power amplifier that amplifies an RF signal. The envelope tracker includes an error amplifier that controls a voltage level of a power amplifier supply voltage of the power amplifier based on amplifying a difference between a reference signal and an envelope signal indicating an envelope of the RF signal. The envelope tracker further includes a multi-level switching circuit that generates an error amplifier supply voltage based on sensing a current of the error amplifier, and uses the error amplifier supply voltage to power the error amplifier.
    Type: Grant
    Filed: December 30, 2020
    Date of Patent: October 18, 2022
    Assignee: Skyworks Solutions, Inc.
    Inventors: Serge Francois Drogi, Florinel G. Balteanu, David Richard Pehlke
  • Patent number: 11476814
    Abstract: An improved transformer based switch for PALNA applications. The transformer based switch having an input single pole port and a circuit with at least one transformer and at least one switch configured to connect portions of the transformer to ground or to short the transformer. The primary side of the transformer being connected to the input port and the secondary side of the transformer being connected to an output port.
    Type: Grant
    Filed: December 11, 2018
    Date of Patent: October 18, 2022
    Assignee: Teknologian tukimuskeskus VTT Oy
    Inventors: Mikko Varonen, Jan Saijets, Jan Holmberg
  • Patent number: 11476807
    Abstract: A power amplifier module includes a first amplifier circuit that amplifies a radio frequency signal with a first gain corresponding to a first control signal to generate a first amplified signal; a second amplifier circuit that amplifies the first amplified signal with a second gain corresponding to a second control signal to generate a second amplified signal; and a control unit that generates the first control signal and the second control signal. The second control signal is a control signal for increasing a power-supply voltage for the second amplifier circuit as a peak-to-average power ratio of the radio frequency signal increases. The first control signal is a control signal for controlling the first gain of the first amplifier circuit so that a variation in the second gain involved in a variation in the power-supply voltage for the second amplifier circuit is compensated for.
    Type: Grant
    Filed: October 28, 2020
    Date of Patent: October 18, 2022
    Assignee: MURATA MANUFACTURING CO., LTD.
    Inventors: Shigeki Koya, Takayuki Tsutsui, Yasunari Umemoto, Isao Obu, Satoshi Tanaka
  • Patent number: 11469713
    Abstract: A power amplifier module includes first and second amplifiers, a first bias circuit, and an adjusting circuit. The first amplifier amplifies a first signal. The second amplifier amplifies a second signal based on an output signal from the first amplifier. The first bias circuit supplies a bias current to the first amplifier via a current path on the basis of a bias drive signal. The adjusting circuit includes an adjusting transistor having first, second, and third terminals. A first voltage based on a power supply voltage is supplied to the first terminal. A second voltage based on the bias drive signal is supplied to the second terminal. The third terminal is connected to the current path. The adjusting circuit adjusts the bias current on the basis of the power supply voltage supplied to the first amplifier.
    Type: Grant
    Filed: January 11, 2021
    Date of Patent: October 11, 2022
    Assignee: MURATA MANUFACTURING CO., LTD.
    Inventor: Kenichi Shimamoto
  • Patent number: 11469717
    Abstract: Microwave amplifiers tolerant to electrical overstress are provided. In certain embodiments, a monolithic microwave integrated circuit (MMIC) includes a signal pad that receives a radio frequency (RF) signal, a ground pad, a balun including a primary section that receives the RF signal and a secondary section that outputs a differential RF signal, an amplifier that amplifies the differential RF signal, and a plurality of decoupling elements, some of them electrically connected between the primary section and the ground pad, others electrically connected in the secondary section to a plurality of the amplifier's nodes, and operable to protect the amplifier from electrical overstress. Such electrical overstress events can include electrostatic discharge (ESD) events, such as field-induced charged-device model (FICDM) events, as well as other types of overstress conditions.
    Type: Grant
    Filed: April 3, 2020
    Date of Patent: October 11, 2022
    Assignee: Analog Devices International Unlimited Company
    Inventors: Srivatsan Parthasarathy, Javier A. Salcedo, Miguel Chanca
  • Patent number: 11463061
    Abstract: An improved method of providing high burst power to audio amplifiers from limited power sources, using parallel power paths to increase system efficiency without need for a power path controller, thus utilizing a simplified circuit operation and maximizing average power available for both the amplifier and supporting circuitry.
    Type: Grant
    Filed: February 9, 2021
    Date of Patent: October 4, 2022
    Assignee: BIAMP SYSTEMS, LLC
    Inventors: David F. Baretich, Simon J. Broadley