Abstract: Systems and methods are provided for amplifying multiple input signals to generate multiple output signals. An example system includes a first channel, a second channel, and a third channel. The first channel is configured to receive one or more first input signals, process information associated with the one or more first input signals and a first ramp signal, and generate one or more first output signals. The second channel is configured to receive one or more second input signals, process information associated with the one or more second input signals and a second ramp signal, and generate one or more second output signals. The first ramp signal corresponds to a first phase. The second ramp signal corresponds to a second phase. The first phase and the second phase are different.

Abstract: A balun is disclosed and includes a dielectric substrate defining a first surface and a second surface. The balun includes a first output port including a first output ground portion and first output power portion; a second output port including a second output ground portion and a second output power portion; and an input port including an input ground portion and input power portion. The first output ground portion, the second output ground portion, and the input ground portion are coupled at a ground junction portion. The first output power portion, the second output power portion, and the input power portion are coupled at a power junction portion. The first output power portion, the second output power portion, and the input power portion are positioned on the first surface. The first output ground portion, the second output ground portion, and the input ground portion are positioned on the second surface.

Abstract: A power control circuit includes: a voltage-current converter and a programmable current amplifier; the voltage-current converter is configured to detect an inputted output power control signal, and to convert the output power control signal to a control current and output same; and the programmable current amplifier is configured to receive the control current and output the amplified control current as a bias current of the power amplifier connected to the power control circuit.

Abstract: A power amplifier includes an amplifier circuit group including multiple amplifier circuits, a distributing circuit that distributes an input signal to each of the multiple amplifier circuits, and a combining circuit that combines output signals from the multiple amplifier circuits. Each of the multiple amplifier circuits includes an amplifier transistor including multiple cell transistors having different sizes and bias circuits that supply bias current to the respective cell transistors.

Abstract: The application describes a transimpedance amplifier circuit having a first circuit branch extending between first and second supply nodes. An input NMOS transistor is located in the first circuit branch, with its drain terminal coupled to the first supply node via a load resistor, its source terminal coupled to the second supply node and its gate terminal coupled to an input node for receiving an input signal. The circuit includes a PMOS transistor having its source terminal coupled to a third supply node, its drain terminal coupled to the first circuit branch, at a node in a part of the first circuit branch extending from the drain terminal of the input transistor to the load resistor, and its gate terminal coupled to the input node. A drain current of the PMOS transistor contributes a proportion but not all of a drain current for input NMOS transistor.

Abstract: A differential pair of transistors receives input voltages. Current mirror transistors and cascode transistors are coupled to the differential pair of transistors. The differential pair of transistors is coupled between the cascode transistors and a tail transistor that draws a first bias current from a tail node, the first bias current having a magnitude equal to a product of a total bias current and a constant that is less than one. A first current source transistor draws a second bias current from a node between the differential pair and cascode transistors so the second bias current bypasses one transistor of the differential pair of transistors. The second bias current has a magnitude equal to a product of the total bias current and a value equal to one minus the constant. An output stage is biased by an output at node between the cascode transistors and the current mirror transistors.

Abstract: A circuit (e.g., implemented as part of a controller area network (CAN) bus receiver includes a pre-amplifier stage having first and second outputs. The circuit also includes a comparator having first and second inputs. The first input is coupled to the first output of the pre-amplifier stage, and the second input is coupled to the second output of the pre-amplifier stage. The comparator includes an input differential transistor pair, a second pair of transistors coupled to the input differential transistor pair in a cascode configuration, and a push-pull output stage coupled to the second pair of transistors.

Abstract: A circuit includes an analog-to-digital converter (ADC). The circuit also includes an analog front end (AFE) having an AFE input and an AFE output. The AFE output is coupled the ADC's input. The AFE includes a programmable gain amplifier (PGA) having a first PGA input and a second PGA input. The PGA includes a first operational amplifier (OP AMP) with first and second OPAMP inputs. The AFE also including a programmable resistance circuit having a first programmable resistance circuit input and first and second programmable resistance circuit outputs. The first programmable resistance circuit input is coupled to the first and second PGA inputs. The programmable resistance circuit includes a resistor network having first and second balance resistances. The first balance resistance is coupled to the first and second OP AMP inputs, and the second balance resistance is coupled to the first and second OP AMP inputs.

Abstract: A power amplifier includes an amplifying circuit, including an amplifying transistor configured to amplify an input signal and configured to output an output signal, a bias circuit, including a bias transistor comprising an emitter configured to provide a bias current into a base of the amplifying transistor, and a base into which a control current is input, and an overcurrent protecting circuit configured to bypass the control current into a ground, according to a current level of the output signal.

Abstract: A power amplifier having: a plurality of N amplifier modules, where N is an integer greater than one; an M:N power splitter having M inputs, where M is an integer less than N, and N outputs, each one of the N outputs being coupled to an input of a corresponding one of the plurality of N power amplifiers; a plurality of M delay lines, each one the M delay lines having an output coupled to a corresponding one of the M inputs of the M:N power splitter, each one of the plurality of M delay lines being coupled to a common input of the power amplifier.

Abstract: Support circuitry for a power transistor includes a feedback switching element and switching control circuitry. The feedback switching element is coupled between a Kelvin connection node and a second power switching node. The switching control circuitry is configured to cause the feedback switching element to couple the Kelvin connection node to the second power switching node after the power transistor is switched from a blocking mode of operation to a conduction mode of operation and cause the feedback switching element to isolate the Kelvin connection node from the second power switching node before the power transistor is switched from the conduction mode of operation to the blocking mode of operation.

Abstract: An exemplary embodiment of the invention relates to an electrical amplifier comprising a differential preamplifier having a first output port and a second output port; and a downstream amplifier stage having a first output unit and a second output unit; wherein the first output unit is connected to the first output port of the differential preamplifier and the second output unit is connected to the second output port of the differential preamplifier; and wherein a negative impedance converter is electrically located in at least one of said differential preamplifier and said downstream amplifier stage.

Abstract: Included is a compensation circuit having one end connected to another end of a first output circuit and another end of a second output circuit and another end grounded, the compensation circuit having an electrical length of 90 degrees at a first operation frequency and an electrical length of 45 degrees at a second operation frequency which is half of the first operation frequency.

Abstract: A differential amplifier is provided. The differential amplifier includes: a differential input circuit, adjusting a second current and a third current flowing into the differential input circuit according to a first input voltage, a second input voltage, and a first current; a first current source circuit, generating the first current according to a first reference voltage; a current-mirror circuit, generating a fifth current according to a fourth current; a second current source circuit, generating a sixth current and a seventh current according to a second reference voltage; and an impedance circuit, coupled to the current-mirror circuit and a ground terminal, the differential amplifier having a low output voltage error.

Abstract: Disclosed herein is a circuit including a differential amplifier having a pair of input transistors coupled in a differential arrangement between adjustable current sources and receiving input differential signals from a pair of input voltage regulators. The adjustable current sources are configured to source more current to the pair of input transistors than current that is sunk from the pair of input transistors. A first amplifier has inputs coupled to receive differential output voltages from the differential amplifier. A second amplifier has inputs coupled to receive amplified differential output voltages from the first amplifier. A low pass filter has inputs coupled to receive further amplified differential output voltages from the second amplifier and produce final differential output voltages.

Abstract: An amplifier circuit includes a potential relation between a common emitter amplifier circuit (amplifier circuit body) including an NPN transistor (bipolar transistor) and a clamp circuit which maintains a potential relation between a base-collector of the NPN transistor of the common emitter amplifier circuit. The clamp circuit includes a level shift circuit and a clamp diode for suppressing a decrease in the collector potential of the NPN transistor of the common emitter amplifier circuit.

Abstract: A radio frequency module includes a mounting substrate, a low-noise amplifier including an amplifying element and amplifying a radio frequency signal, and an impedance matching circuit including an integrated first inductor, in which the first inductor is connected to an input terminal of the low-noise amplifier, the low-noise amplifier and the impedance matching circuit are laminated in a direction perpendicular to a main surface of the mounting substrate, and a first multilayer body on which the low-noise amplifier and the impedance matching circuit are laminated is mounted on the main surface.

Abstract: A Doherty amplifier module includes a substrate, an RF signal splitter, a carrier amplifier die, and first and second peaking amplifier dies. The RF signal splitter divides an input RF signal into first, second, and third input RF signals, and conveys the input RF signals to splitter output terminals. The carrier amplifier die includes one or more first power transistors configured to amplify, along a carrier signal path, the first input RF signal to produce an amplified first RF signal. The peaking amplifier dies each include one or more additional power transistors configured to amplify, along first and second peaking signal paths, the second and third input RF signals to produce amplified second and third RF signals. The dies are coupled to the substrate so that the RF signal paths through the carrier and one or more of the peaking amplifier dies extend in substantially different (e.g., orthogonal) directions.

Abstract: An output OUT is coupled to a load. A high-side transistor MH is arranged such that its source is coupled to a power supply line, and such that its drain is coupled to an output terminal OUT. A first OCP circuit compares a first current detection signal ICS1 that corresponds to a current ISRC that flows through the high-side transistor MH with a first threshold value IOCP having a positive correlation with a power supply voltage VDD of a power supply line, and generates a first OCP signal SOCP that indicates the comparison result. A driving circuit latch-stops the driving operation of the high-side transistor MH according to the first OCP signal SOCP.

Abstract: An amplifying device includes a self-excited class D amplifier circuit and a band elimination filter. The self-excited class D amplifier circuit includes a modulation circuit that is configured to apply self-oscillating pulse modulation to an audio signal. The modulation circuit is configured to receive, from a signal generation circuit, a supply of a synchronizing signal with which the self-oscillation synchronizes. The band elimination filter is configured to reduce components that belong to a frequency band including a frequency of the synchronizing signal, in an output signal from the self-excited class D amplifier circuit.