Patents Examined by Paul Budd
  • Patent number: 9887207
    Abstract: A monolithic three dimensional NAND string includes a plurality of control gate electrodes extending substantially parallel to a major surface of a substrate, a memory opening extending substantially perpendicular to the major surface of the substrate and filled with a memory opening material including a memory film, and a dummy opening extending substantially perpendicular to the major surface of the substrate and filled with a dummy channel material which is different from the memory opening material. The dummy channel material has a higher Young's modulus than the memory opening material to offset warpage of the substrate due to the one of compressive and tensile stress imposed by the plurality of control gate electrodes on the substrate.
    Type: Grant
    Filed: August 18, 2014
    Date of Patent: February 6, 2018
    Assignee: SANDISK TECHNOLOGIES LLC
    Inventors: Yanli Zhang, Raghuveer S. Makala, Johann Alsmeier, Yao-Sheng Lee, Tiger Xu
  • Patent number: 9570465
    Abstract: An integrated circuit, including: a first cell, including: FDSOI transistors; a UTBOX layer lying beneath the transistors; a first well lying beneath the insulator layer and beneath the transistors, the first well having a first type of doping; a first ground plane having a second type of doping, located beneath one of the transistors and between the insulator layer and the first well; a first STI separating the transistors and crossing the insulator layer; a first conductive element forming an electrical connection between the first well and the first ground plane, located under the first STI; a second cell including a second well; a second STI separating the cells, crossing the insulator layer and reaching the bottom of the first and second wells.
    Type: Grant
    Filed: February 28, 2013
    Date of Patent: February 14, 2017
    Assignees: COMMISSARIAT A L'ENERGIE ATOMIQUE ET AUX ENERGIES ALTERNATIVES, INTERNATIONAL BUSINESS MACHINES CORPORATION, STMicroelectronics, Inc.
    Inventors: Maud Vinet, Kangguo Cheng, Bruce Doris, Laurent Grenouillet, Ali Khakifirooz, Yannick Le Tiec, Qing Liu
  • Patent number: 9520353
    Abstract: A metal-insulation-metal (MIM) device including a first metal layer, a first insulation layer, a second metal layer, and a second insulation layer is provided. The first insulation layer is disposed on the first metal layer. The second metal layer is disposed on a part of the first insulation layer. The second insulation layer is disposed on a side wall of the second metal layer and on another part of the first insulation layer. A width of the first insulation layer under the second metal layer and the second insulation layer parallel to the first metal layer is greater than a with of the second metal layer parallel to the first metal layer.
    Type: Grant
    Filed: May 12, 2015
    Date of Patent: December 13, 2016
    Assignee: HIMAX TECHNOLOGIES LIMITED
    Inventors: Hung-Sui Lin, Mao-Hsiung Lin
  • Patent number: 9502551
    Abstract: A semiconductor device includes a first semiconductor layer, a second semiconductor layer formed over the first semiconductor layer, a gate insulating film contacting the second semiconductor layer, and a gate electrode facing the second semiconductor layer via the gate insulating film. The first semiconductor layer includes an Alx?1-xN layer (? includes Ga or In, and 0<x<1), and the second semiconductor layer includes an Aly?1-yN layer (0?y<1), in which y of the Aly?1-yN layer forming the second semiconductor layer increases at least in a region under the gate electrode as a position where y is measured approaches the first semiconductor layer.
    Type: Grant
    Filed: August 18, 2015
    Date of Patent: November 22, 2016
    Assignee: RENESAS ELECTRONICS CORPORATION
    Inventors: Yasuhiro Okamoto, Tatsuo Nakayama, Takashi Inoue, Hironobu Miyamoto
  • Patent number: 9472635
    Abstract: A silicon carbide semiconductor device includes a silicon carbide substrate, a main electrode, a first barrier layer, and an interconnection layer. The main electrode is directly provided on the silicon carbide substrate. The first barrier layer is provided on the main electrode, and is made of a conductive material containing no aluminum. The interconnection layer is provided on the first barrier layer, is separated from the main electrode by the first barrier layer, and is made of a material containing aluminum.
    Type: Grant
    Filed: February 4, 2014
    Date of Patent: October 18, 2016
    Assignee: Sumitomo Electric Industries, Ltd.
    Inventors: Shunsuke Yamada, Taku Horii, Masaki Kijima
  • Patent number: 9450005
    Abstract: An image pickup device according to the present disclosure includes a first pixel and a second pixel each including a photodetection section and a light condensing section, the photodetection section including a photoelectric conversion element, the light condensing section condensing incident light toward the photodetection section, the first pixel and the second pixel being adjacent to each other and each having a step part on a photodetection surface of the photodetection section, in which at least a part of a wall surface of the step part is covered with a first light shielding section.
    Type: Grant
    Filed: March 27, 2014
    Date of Patent: September 20, 2016
    Assignee: Sony Corporation
    Inventors: Takeshi Yanagita, Suguru Saito, Kaoru Koike
  • Patent number: 9406529
    Abstract: A finFET structure, and method of forming such structure, in which a germanium enriched nanowire is located in the channel region of the FET, while simultaneously having silicon-germanium fin in the source/drain region of the finFET.
    Type: Grant
    Filed: March 5, 2015
    Date of Patent: August 2, 2016
    Assignee: International Business Machines Corporation
    Inventors: Kevin K. Chan, Pouya Hashemi, Ali Khakifirooz, John A. Ott, Alexander Reznicek
  • Patent number: 9406668
    Abstract: A power semiconductor element includes: a main transistor including a first gate electrode, a first drain electrode, and a first source electrode; a sensor transistor including a second gate electrode, a second drain electrode, and a second source electrode; and a gate switch transistor including a third gate electrode, and a third drain electrode, a third source electrode. The first gate electrode, the second gate electrode, and the third drain electrode are connected, the first drain electrode and the second drain electrode are connected, the first source electrode and the second source electrode are connected via a sensor resistor, the first source electrode and the third source electrode are connected, the second source electrode and the third gate electrode are connected via a switch resistor, and the main transistor, the sensor transistor, and the gate switch transistor are formed with a nitride semiconductor.
    Type: Grant
    Filed: February 25, 2014
    Date of Patent: August 2, 2016
    Assignee: PANASONIC INTELLECTUAL PROPERTY MANAGEMENT CO., LTD.
    Inventors: Shuichi Nagai, Daisuke Ueda, Tatsuo Morita, Tetsuzo Ueda
  • Patent number: 9401472
    Abstract: Programmable impedance elements structures, devices and methods are disclosed. Methods can include: forming a first electrode layer within an electrode opening that extends through a cap layer; planarizing to expose a top of the cap layer; cleaning the exposed top surface of the cap layer to remove residual species from previous process steps. Additional methods can include forming at least a base ion conductor layer having an active metal formed therein that may ion conduct within the ion conductor layer; and forming an inhibitor material that mitigates agglomeration of the active metal within the base ion conductor layer as compared to the active metal alone. Programmable impedance elements and/or devices can have switching material and electrodes parallel to both bottoms and sides of a cell opening formed in a cell dielectric. Other embodiments can include an ion conductor layer having an alloy of an active metal, or two ion conductor layers in contact with an active electrode.
    Type: Grant
    Filed: September 23, 2011
    Date of Patent: July 26, 2016
    Assignee: Adesto Technologies Corporation
    Inventors: Chakravarthy Gopalan, Antonio R. Gallo, Yi Ma
  • Patent number: 9397144
    Abstract: According to one embodiment, a non-volatile semiconductor memory device includes: a semiconductor substrate; a plurality of first lines; a plurality of second lines; and a plurality of non-volatile memory cells arranged at positions where the plurality of first lines intersect with the plurality of second lines, wherein each of the plurality of non-volatile memory cells includes a resistance change element and a rectifying element connected in series to the resistance change element, and a resistance change film continuously extending over the plurality of second lines is arranged between the plurality of first lines and the plurality of second lines, and the resistance change element includes a portion where the first line intersect with the second line in the resistance change film.
    Type: Grant
    Filed: September 11, 2014
    Date of Patent: July 19, 2016
    Assignee: Kabushiki Kaisha Toshiba
    Inventor: Hiroyuki Nansei
  • Patent number: 9385240
    Abstract: A memory device includes a substrate, a first doped region, composite structures, word lines, and a charge storage layer. The first doped region is disposed on a surface of the substrate. The composite structures are disposed on the first doped region. Each composite structure includes two semiconductor fin structures and a dielectric layer. Each semiconductor fin structure includes a second doped region disposed at an upper portion of the semiconductor fin structure and a body region disposed between the second doped region and the first doped region. The dielectric layer is disposed between the semiconductor fin structures. The word lines are disposed on the substrate. Each word line covers a partial sidewall and a partial top of each composite structure. The charge storage layer is disposed between the composite structures and the word lines.
    Type: Grant
    Filed: March 3, 2015
    Date of Patent: July 5, 2016
    Assignee: MACRONIX International Co., Ltd.
    Inventors: Chih-Chieh Cheng, Shih-Guei Yan, Wen-Jer Tsai, Nan-Heng Lu
  • Patent number: 9379178
    Abstract: A method for manufacturing a semiconductor device includes a capacitor element in which a capacitance dielectric film is provided between an upper electrode film and a lower electrode film, includes forming the lower electrode film over the semiconductor substrate, forming the capacitance dielectric film over the lower electrode film, and forming the upper electrode film over the capacitance dielectric film, wherein, an entire surface layer of the lower electrode film is formed of a polycrystalline titanium nitride. At the portion of the capacitance dielectric film where directly contacting the entire surface layer of the lower electrode is formed of a polycrystalline metal oxide, and the polycrystalline metal oxide is formed by an ALD method and inherits a crystallinity of the polycrystalline titanium nitride.
    Type: Grant
    Filed: August 26, 2015
    Date of Patent: June 28, 2016
    Assignee: Renesas Electronics Corporation
    Inventors: Youichi Yamamoto, Naomi Fukumaki, Misato Sakamoto, Yoshitake Kato
  • Patent number: 9379104
    Abstract: Methods for preparing a FinFET device with a protection diode formed prior to M1 formation and resulting devices are disclosed. Embodiments include forming plural fins on a substrate, with a STI region between adjacent fins; forming a dummy gate stack over and perpendicular to the fins, the gate stack including a dummy gate over a dummy gate insulating layer; forming sidewall spacers on opposite sides of the dummy gate stack; forming source/drain regions at opposite sides of the dummy gate stack; forming an ILD over the STI regions between fins; removing the dummy gate stack forming a gate cavity; forming a gate dielectric in the gate cavity; removing the gate dielectric from the gate cavity in a protection diode area, exposing an underlying fin; implanting a dopant into the exposed fin; and forming a RMG in the gate cavity, wherein a protection diode is formed in the protection diode area.
    Type: Grant
    Filed: March 5, 2015
    Date of Patent: June 28, 2016
    Assignee: GLOBALFOUNDRIES INC.
    Inventor: Xusheng Wu
  • Patent number: 9379165
    Abstract: A semiconductor memory device according to an embodiment described below comprises: first lines arranged in a first direction perpendicular to a main surface of a substrate and extending in a second direction crossing the first direction; second lines arranged in the second direction, extending in the first direction, and intersecting the first lines; memory cells disposed at intersections of the first lines and the second lines; and an interlayer insulating film provided between the second lines. The interlayer insulating film has an air gap extending continuously in the first direction so as to intersect at least some of the first lines aligned along the first direction. The interlayer insulating film also includes an insulating film positioned above the air gap and having a curved surface that protrudes toward a direction of the substrate.
    Type: Grant
    Filed: April 28, 2014
    Date of Patent: June 28, 2016
    Assignee: KABUSHIKI KAISHA TOSHIBA
    Inventors: Atsushi Yoshida, Hiroshi Kanno, Takayuki Tsukamoto, Takamasa Okawa, Hideyuki Tabata
  • Patent number: 9362301
    Abstract: A nonvolatile memory device includes a pipe insulation layer having a pipe channel hole, a pipe gate disposed over the pipe insulation layer, a pair of cell strings each having a columnar cell channel, and a pipe channel coupling the columnar cell channels and surrounding inner sidewalls and a bottom of the pipe channel hole.
    Type: Grant
    Filed: December 8, 2014
    Date of Patent: June 7, 2016
    Assignee: SK Hynix Inc.
    Inventors: Ki-Hong Lee, Kwon Hong, Dae-Gyu Shin
  • Patent number: 9362224
    Abstract: An electrical fuse is provided. The electrical fuse includes an anode formed on a substrate, a cathode formed on the substrate, a fuse link connecting the anode and the cathode to each other, a first contact formed on the anode, and a second contact formed on the cathode and arranged closer to the fuse link than the first contact.
    Type: Grant
    Filed: June 25, 2013
    Date of Patent: June 7, 2016
    Assignee: Magnachip Semiconductor, Ltd.
    Inventors: SeongDo Jeon, JinSeop Shim, JaeWoon Kim, SungRyul Baek, JongSoo Kim, YunHie Choi, SuJin Kim, SungBum Park
  • Patent number: 9356146
    Abstract: A semiconductor device including a gate electrode disposed on a semiconductor substrate and source/drain regions disposed at both sides of the gate electrode, the source/drain regions being formed by implanting impurities. The source/drain regions include an epitaxial layer formed by epitaxially growing a semiconductor material having a different lattice constant from that of the semiconductor substrate in a recessed position at a side of the gate electrode, and a diffusion layer disposed in a surface layer of the semiconductor substrate.
    Type: Grant
    Filed: March 19, 2015
    Date of Patent: May 31, 2016
    Assignee: SONY CORPORATION
    Inventor: Takuji Matsumoto
  • Patent number: 9343310
    Abstract: An apparatus and a method are disclosed for forming electrical conductors and/or semiconductors on a glass substrate. The electrical conductors and/or semiconductors are formed by applying a conducting material or a semiconductor material to a surface of the glass substrate and irradiating the interface with a focused laser beam transmitted through the glass. An electrical conductor may be formed on a glass substrate or a semiconductor substrate to provide an electrical antenna for radio frequency communication.
    Type: Grant
    Filed: June 26, 2013
    Date of Patent: May 17, 2016
    Inventors: Nathaniel R Quick, Michael C Murray
  • Patent number: 9305849
    Abstract: A monolithic three dimensional NAND string includes a semiconductor channel, an end part of the semiconductor channel extending substantially perpendicular to a major surface of a substrate, a plurality of control gate electrodes extending substantially parallel to the major surface of the substrate, a charge storage material layer located between the plurality of control gate electrodes and the semiconductor channel, a tunnel dielectric located between the charge storage material layer and the semiconductor channel, and a blocking dielectric containing a plurality of clam-shaped portions each having two horizontal portions connected by a vertical portion. Each of the plurality of control gate electrodes are located at least partially in an opening in the clam-shaped blocking dielectric, and a plurality of discrete cover oxide segments embedded in part of a thickness of the charge storage material layer and located between the blocking dielectric and the charge storage material layer.
    Type: Grant
    Filed: November 12, 2014
    Date of Patent: April 5, 2016
    Assignee: SANDISK TECHNOLOGIES INC.
    Inventors: Masanori Tsutsumi, Shigehiro Fujino, Sateesh Koka, Senaka Kanakamedala, Yanli Zhang, Raghuveer S. Makala, Rahul Sharangpani, George Matamis, Wei Zhao
  • Patent number: 9306161
    Abstract: A method of forming a conductive bridging memory cell can include forming an active electrode layer above a barrier layer formed on a lower conductive layer; forming at least one ion conductor layer over an active electrode layer; incorporating conductive ions into the ion conductor layer to create a switch memory layer that changes impedance in response to an electric field; and the active electrode layer is a source of conductive ions for the ion conductor, and the barrier layer substantially prevents a movement of conductive ions therethrough.
    Type: Grant
    Filed: March 18, 2013
    Date of Patent: April 5, 2016
    Assignee: Adesto Technologies Corporation
    Inventors: Yi Ma, Chakravarthy Gopalan, Antonio R. Gallo, Janet Wang