Patents Examined by Paul Budd
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Patent number: 9299698Abstract: A semiconductor structure includes first, second, and third transistor elements each having a first screening region concurrently formed therein. A second screening region is formed in the second and third transistor elements such that there is at least one characteristic of the screening region in the second transistor element that is different than the second screening region in the third transistor element. Different characteristics include doping concentration and depth of implant. In addition, a different characteristic may be achieved by concurrently implanting the second screening region in the second and third transistor element followed by implanting an additional dopant into the second screening region of the third transistor element.Type: GrantFiled: June 25, 2013Date of Patent: March 29, 2016Assignee: Mie Fujitsu Semiconductor LimitedInventors: Dalong Zhao, Teymur Bakhishev, Lance Scudder, Paul E. Gregory, Michael Duane, U. C. Sridharan, Pushkar Ranade, Lucian Shifren, Thomas Hoffmann
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Patent number: 9299734Abstract: A method of preparing an active pixel cell on a substrate includes exerting a first stress on the substrate by forming a shallow trench isolation (STI) structure in the substrate. The method further includes testing the stressed substrate using Raman spectroscopy at a plurality of locations on the stress substrate. The method further includes depositing a stress layer having a second stress on the substrate. The stress layer covers devices of the active pixel cell that are on the substrate and the devices include a photodiode next to the STI and a transistor, and the deposition of the stress layer results in the second stress being exerted on the substrate, the second stress countering the first stress.Type: GrantFiled: September 4, 2013Date of Patent: March 29, 2016Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Ru-Shang Hsiao, Nai-Wen Cheng, Chung-Te Lin, Chien-Hsien Tseng, Shou-Gwo Wuu
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Patent number: 9287136Abstract: Field effect transistors fabricated using atomic layer doping processes are disclosed. In accordance with an embodiment of an atomic layer doping method, a semiconducting surface and a dopant gas mixture are prepared. Further, a dopant layer is grown on the semiconducting surface by applying the dopant gas mixture to the semiconducting surface under a pressure that is less than 500 Torr and a temperature that is between 300° C. and 750° C. The dopant layer includes at least 4×1020 active dopant atoms per cm3 that react with atoms on the semiconducting surface such that the reacted atoms increase the conductivity of the semiconducting surface.Type: GrantFiled: September 7, 2012Date of Patent: March 15, 2016Assignee: GLOBALFOUNDRIES INC.Inventors: Kevin K. Chan, Young-Hee Kim, Isaac Lauer, Ramachandran Muralidhar, Dae-Gyu Park, Xinhui Wang, Min Yang
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Patent number: 9281397Abstract: A semiconductor device (e.g., field effect transistor (FET)) having an asymmetric feature, includes a first gate formed on a substrate, first and second diffusion regions formed in the substrate on a side of the first gate, and first and second contacts which contact the first and second diffusion regions, respectively, the first contact being asymmetric with respect to the second contact.Type: GrantFiled: January 17, 2014Date of Patent: March 8, 2016Assignee: GLOBALFOUNDRIES INC.Inventors: Josephine Chang, Isaac Lauer, Chung-Hsun Lin, Jeffrey Sleight
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Patent number: 9281315Abstract: A memory structure and a method for manufacturing the same are provided. The memory structure comprises a substrate, stacks, memory layers, a conductive material and conductive lines. The stacks are positioned on the substrate. The stacks are separated from each other by trenches. Each of the stacks comprises alternately stacked conductive stripes and insulating stripes. The memory layers conformally cover the stacks respectively. The conductive material is positioned in the trenches and on the stacks. The conductive material in the trenches forms one or more holes in each of the trenches. The conductive lines are positioned on the conductive material. Each of the conductive lines comprises a first portion and a second portion connected to each other, the first portion extends along a direction perpendicular to an extending direction of the stacks, and the second portion extends along the extending direction of the stacks.Type: GrantFiled: March 3, 2015Date of Patent: March 8, 2016Assignee: MACRONIX INTERNATIONAL CO., LTD.Inventors: Teng-Hao Yeh, Yen-Hao Shih, Chih-Wei Hu
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Patent number: 9263473Abstract: In a semiconductor device which conducts multilevel writing operation and a driving method thereof, a signal line for controlling on/off of a writing transistor for conducting a writing operation on a memory cell using a transistor including an oxide semiconductor layer is disposed along a bit line, and a multilevel writing operation is conducted with use of, also in a writing operation, a voltage which is applied to a capacitor at a reading operation. Because an oxide semiconductor material that is a wide gap semiconductor capable of sufficiently reducing off-state current of a transistor is used, data can be held for a long period.Type: GrantFiled: July 23, 2014Date of Patent: February 16, 2016Assignee: Semiconductor Energy Laboratory Co., Ltd.Inventor: Tatsuya Ohnuki
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Patent number: 9257502Abstract: In one general aspect, a power semiconductor device can include a semiconductor substrate of a first conductivity type, and a semiconductor layer of a second conductivity type disposed on the semiconductor substrate. The semiconductor layer can include a high voltage unit, a low voltage unit disposed around the high voltage unit, and a level shift unit disposed between the high voltage unit and the low voltage unit. The power semiconductor device can include a first isolation region of the first conductivity type disposed between the high voltage unit and the level shift unit, and a second isolation region of the first conductivity type disposed between the low voltage unit and the level shift unit where the first isolation region and the second isolation region each are vertically aligned in the semiconductor layer and each extends to at least the semiconductor substrate.Type: GrantFiled: June 26, 2013Date of Patent: February 9, 2016Assignee: Fairchild Korea Semiconductor Ltd.Inventors: Min-suk Kim, Sun-hak Lee, Jin-woo Moon, Hye-mi Kim
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Patent number: 9257549Abstract: A semiconductor device having a semiconductor body, a source metallization arranged on a first surface of the semiconductor body and a trench including a first trench portion and a second trench portion and extending from the first surface into the semiconductor body is provided. The semiconductor body further includes a pn-junction formed between a first semiconductor region and a second semiconductor region. The first trench portion includes an insulated gate electrode which is connected to the source metallization, and the second trench portion includes a conductive plug which is connected to the source metallization and to the second semiconductor region.Type: GrantFiled: April 25, 2013Date of Patent: February 9, 2016Assignee: Infineon Technologies Austria AGInventor: Franz Hirler
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Patent number: 9231099Abstract: A semiconductor device includes: a first conductivity type semiconductor substrate; and a plurality of second conductivity type semiconductor regions, the respective second conductivity type semiconductor regions being embedded in a plurality of stripe shaped trenches formed in the semiconductor substrate so that the respective second conductivity type semiconductor regions are extended in the row direction or the column direction in parallel with a first principal surface of the semiconductor substrate and are spaced in a fixed gap mutually. The semiconductor substrate and the plurality of the semiconductor regions are depleted by a depletion layer extended in the direction in parallel to the first principal surface from a plurality of pn junction interfaces, and the respective pn junction interfaces are formed between the semiconductor substrate and the plurality of the semiconductor regions.Type: GrantFiled: November 27, 2009Date of Patent: January 5, 2016Assignee: ROHM CO., LTD.Inventor: Shoji Higashida
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Patent number: 9219070Abstract: A 3-D memory array comprises a plurality of elevationally extending strings of memory cells. An array of select devices is elevationally over and individually coupling with individual of the strings. The select devices individually comprise a channel, gate dielectric proximate the channel, and gate material proximate the gate dielectric. The individual channels are spaced from one another. The gate material comprises a plurality of gate lines running along columns of the spaced channels elevationally over the strings. Dielectric material is laterally between immediately adjacent of the gate lines. The dielectric material and the gate lines have longitudinally non-linear edges at an interface relative one another. Additional embodiments are disclosed.Type: GrantFiled: February 5, 2013Date of Patent: December 22, 2015Assignee: Micron Technology, Inc.Inventors: Deepak Thimmegowda, Brian Cleereman, Khaled Hasnat
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Patent number: 9212051Abstract: Systems and methods for forming MEMS assemblies incorporating getters are described. One such method for forming and bonding to a microelectromechanical systems (MEMS) assembly includes providing a first MEMS wafer including a metal layer on an inner surface and one or more cavities for forming a MEMS component, attaching a MEMS capping wafer, having at least one through hole via, to the inner surface of the first MEMS wafer thereby forming at least one encapsulated MEMs component within the first MEMS wafer, and bonding a wire to the metal layer through an open end of the at least one through hole via.Type: GrantFiled: August 4, 2011Date of Patent: December 15, 2015Assignee: Western Digital (Fremont), LLCInventors: Pezhman Monadgemi, Lei Wang
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Patent number: 9202784Abstract: A semiconductor integrated circuit device includes a substrate structure layer including a substrate having a well and a diffusion region thereon, an interconnect layer including a pair of power supply lines arranged at a preset spacing from the substrate structure layer; the interconnect layer also including an input side interconnect and an output side interconnect between the pair of power supply lines, a standard cell having a logic circuit on the substrate; the logic circuit being electrically connected to the pair of power supply lines, the input side interconnect and the output side interconnect, and one or more capacitances arranged between the substrate structure layer and the interconnect layer and arranged in a region between the pair of power supply lines, the region being inclusive of a region superposed with the pair of power supply lines.Type: GrantFiled: April 18, 2013Date of Patent: December 1, 2015Assignee: RENESAS ELECTRONICS CORPORATIONInventors: Masatake Wada, Naoki Imakita
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Patent number: 9202909Abstract: A semiconductor device includes a source metallization, a source region of a first conductivity type in contact with the source metallization, a body region of a second conductivity type which is adjacent to the source region. The semiconductor device further includes a first field-effect structure including a first insulated gate electrode and a second field-effect structure including a second insulated gate electrode which is electrically connected to the source metallization. The capacitance per unit area between the second insulated gate electrode and the body region is larger than the capacitance per unit area between the first insulated gate electrode and the body region.Type: GrantFiled: March 28, 2013Date of Patent: December 1, 2015Assignee: Infineon Technologies Austria AGInventors: Oliver Haeberlen, Joachim Krumrey, Franz Hirler, Walter Rieger
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Patent number: 9190610Abstract: A memory device includes a phase change element, which further includes a first phase change layer having a first grain size; and a second phase change layer over the first phase change layer. The first and the second phase change layers are depth-wise regions of the phase change element. The second phase change layer has a second average grain size different from the first average grain size.Type: GrantFiled: December 31, 2013Date of Patent: November 17, 2015Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Chun-Sheng Liang, Tzyh-Cheang Lee, Fu-Liang Yang
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Patent number: 9177908Abstract: The present invention discloses a capacitor in an integrated circuit which comprises a first and second conductive lines substantially parallel to each other and having a thickness equals substantially to a sum of a via thickness and an interconnect thickness, the first and second conductive lines, the via and the interconnect being formed by a single deposition step, and at least one dielectric material in a space horizontally across the first and second conductive lines, wherein the first and second conductive lines serve as two conductive plates of the capacitor, respectively, and the dielectric material serves as an insulator of the capacitor.Type: GrantFiled: April 30, 2007Date of Patent: November 3, 2015Assignee: Taiwan Semiconductor Manufacturing Company, LimitedInventor: Jhon Jhy Liaw
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Patent number: 9171924Abstract: A circuit configuration and methods for controlling parameters of a bipolar junction transistor (BJT) fabricated on a substrate. A bias voltage is electrically coupled to the substrate and can be adjusted to alter the working parameters of a target BJT.Type: GrantFiled: September 19, 2014Date of Patent: October 27, 2015Assignee: GlobalFoundries U.S. 2 LLCInventors: Jin Cai, Tak H. Ning
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Patent number: 9165826Abstract: A method of making a semiconductor device includes forming a high-k dielectric layer over a substrate; and forming a titanium nitride layer over the high-k dielectric layer. The method further includes performing a silicon treatment on the titanium nitride layer to form at least one silicon monolayer over the titanium nitride layer. The method further includes annealing the semiconductor device to form a TiSiON layer over a remaining portion of the titanium nitride layer.Type: GrantFiled: August 25, 2014Date of Patent: October 20, 2015Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Cheng-Hao Hou, Xiong-Fei Yu
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Patent number: 9157807Abstract: A semiconductor device includes a semiconductor layer (2) and a dielectric stack (3) on the semiconductor layer. A plurality of etchant openings (24-1,2 . . . ) are formed through the dielectric stack (3) for passage of etchant for etching a plurality of overlapping sub-cavities (4-1,2 . . . ), respectively. The etchant is introduced through the etchant openings to etch a composite cavity (4) in the semiconductor layer by simultaneously etching the plurality of overlapping sub-cavities into the semiconductor layer.Type: GrantFiled: June 24, 2009Date of Patent: October 13, 2015Assignee: TEXAS INSTRUMENTS INCORPORATEDInventors: Walter B. Meinel, Kalin V. Lazarov, Brian E. Goodlin
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Patent number: 9147459Abstract: In deep submicron memory arrays there is noted a relatively steady on current value and, therefore, threshold values of the transistors comprising the memory cell are reduced. This, in turn, results in an increase in the leakage current of the memory cell. With the use of an ever increasing number of memory cells leakage current must be controlled. Random access memories with a dynamic threshold voltage control scheme implemented with no more than minor changes to the existing MOS process technology is disclosed. The disclosed invention controls the threshold voltage of MOS transistors. Methods for enhancing the impact of the dynamic threshold control technology using this apparatus are also included. The invention is particularly useful for DRAM and NVM devices.Type: GrantFiled: November 2, 2009Date of Patent: September 29, 2015Assignee: SemiSolutions, LLCInventor: Ashok Kumar Kapoor
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Patent number: 9142609Abstract: A semiconductor device has a capacitor element in which a capacitance dielectric film is disposed between an upper electrode film (upper electrode film, an upper electrode film) and a lower electrode film, and the lower electrode film has polycrystalline titanium nitride at least to a portion in contact with the capacitance dielectric film.Type: GrantFiled: January 12, 2011Date of Patent: September 22, 2015Assignee: Renesas Electronics CorporationInventors: Youichi Yamamoto, Naomi Fukumaki, Misato Sakamoto, Yoshitake Kato