Patents Examined by Paul Dinh
  • Patent number: 10417374
    Abstract: A method for designing a system on a target device includes synthesizing the system. The system is placed on the target device. The system is routed on the target device. Register retiming is performed on the system by applying timing analysis constraints, retiming constraints, bound constraints, and ordering constraints when solving for retiming labels that represent a number and direction of register movement along a path between nodes in the system, and arrival times on all nodes in the system to reflect the maximum delay in the system, to improve timing and meet target delay constraints.
    Type: Grant
    Filed: May 9, 2016
    Date of Patent: September 17, 2019
    Assignee: Altera Corporation
    Inventor: Mahesh A. Iyer
  • Patent number: 10417364
    Abstract: Embodiments are directed towards a method to create a reconfigurable interconnect framework in an integrated circuit. The method includes accessing a configuration template directed toward the reconfigurable interconnect framework, editing parameters of the configuration template, functionally combining the configuration template with a plurality of modules from an IP library to produce a register transfer level (RTL) circuit model, generating at least one automated test-bench function, and generating at least one logic synthesis script. Editing parameters of the configuration template includes confirming a first number of output ports of a reconfigurable stream switch and confirming a second number of input ports of the reconfigurable stream switch. Each output port and each input port has a respective architectural composition. The output port architectural composition is defined by a plurality of N data paths including A data outputs and B control outputs.
    Type: Grant
    Filed: February 2, 2017
    Date of Patent: September 17, 2019
    Assignees: STMICROELECTRONICS INTERNATIONAL N.V., STMICROELECTRONICS S.R.L.
    Inventors: Thomas Boesch, Giuseppe Desoli
  • Patent number: 10410917
    Abstract: An electronic design automation method configured to automatically design a semiconductor device includes generating a site-row having a unit height based on a standard cell having the unit height, and generating metal routing tracks which begin at an offset point spaced a specific distance from an origin point of the site-row. The unit height is a non-integer multiple of a spacing of metal lines of one of interconnection layers of the semiconductor device. Using this process, a layout of a plurality of standard cells on a plurality of site-rows, and constituting a Floorplan of the semiconductor device, is generated.
    Type: Grant
    Filed: February 6, 2017
    Date of Patent: September 10, 2019
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Young-San Cha, Dongkyu Youn
  • Patent number: 10387598
    Abstract: An exemplary bitmap file can be provided, which can include, for example, a map of a cell array structure of a memory(ies), a plurality of memory values superimposed on the cell array structure based on a simulated testing of the memory(ies). The memory values may be values being written to the memory(ies) while the memory(ies) is being tested. The memory values may be values in a test pattern(s) being used to test the memory(ies). Each cell in the cell array structure can have a particular memory value superimposed thereon. A cell(s) in the cell array structure may be highlighted, which may correspond to an incorrect memory value.
    Type: Grant
    Filed: September 13, 2017
    Date of Patent: August 20, 2019
    Assignee: Cadence Design Systems, Inc.
    Inventors: Steven Lee Gregor, Norman Robert Card
  • Patent number: 10380283
    Abstract: This application discloses a computing system to select a design block in a circuit design of an electronic device for functional verification result reuse based on isolating operational characteristics of the design block. The computing system can determine whether the selected design block was previously simulated with input stimulus. When the selected design block was previously simulated with the input stimulus, the computing system can bypass the simulation of the design block and utilize an output generated in the previous simulation of the selected design block in response to the input stimulus as a result for the simulation of the design block. When the selected design block was not previously simulated with the input stimulus, the computing system can simulate the selected design block with the input stimulus, and storing an output generated in the simulation of the selected design block for functional verification result reuse.
    Type: Grant
    Filed: February 7, 2017
    Date of Patent: August 13, 2019
    Assignee: Mentor Graphics Corporation
    Inventor: Gaurav Kumar Verma
  • Patent number: 10372866
    Abstract: A data processing system to implement wiring/silicon blockages via parameterized cells (pCells) includes a front end-of-line placement/blockage (FEOL P/B) controller to generate a placement blockage based on an input parameter corresponding to a physical design of an integrated circuit (IC). The FEOL P/B outputs a placement blockage parameter that is stored in a wire track allocation database to indicate the placement blockage. A back end-of-line wiring track (BEOL WT) controller generates a wire track blockage of the IC. A BEOL power track (BEOL PT) controller generates a metal blockage within the wire track blockage. A combination of the metal blockage and the wire track blockage defines a parent-child contract to enable concurrent physical design of the IC without creating shorts and overlaps in a child block of the IC.
    Type: Grant
    Filed: February 13, 2017
    Date of Patent: August 6, 2019
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Christopher J. Berry, Adam R. Jatkowski, Frank Malgioglio, Ryan M. Nett, Joseph J. Palumbo, Sean Salisbury, Gerald L. Strevig, III
  • Patent number: 10360334
    Abstract: Methods and systems assign an alignment context to each of the cells within an integrated circuit layout, from previously established alignment contexts, based on how the different cell widths cause each of the cells to align with adjoining cells. Also, such methods and systems retrieve standard signal delay times for each of the cells from a standard cell library. This allows these methods and systems to adjust the signal delay times for each of the cells based on which alignment context has been assigned to each of the cells, to produce adjusted delay times for each of the cells. Following this, the methods and systems perform a timing analysis of the layout using the adjusted delay times for each of the cells, and output the results of the timing analysis.
    Type: Grant
    Filed: February 9, 2017
    Date of Patent: July 23, 2019
    Assignee: GLOBALFOUNDRIES INC.
    Inventors: Navneet Jain, Mahbub Rashed, Juhan Kim
  • Patent number: 10349758
    Abstract: A secure display stand for a wearable comprises a socket for fixing to a display cabinet or mounting, a bracelet lock for locking around a bracelet or strap of a wearable to be displayed; and a bracket extending from the bracelet lock, the bracket having a charging element for charging of the wearable, wherein the bracelet lock is attached by a retractable cord to the socket.
    Type: Grant
    Filed: February 8, 2016
    Date of Patent: July 16, 2019
    Assignee: Outform Ltd.
    Inventor: Ariel Haroush
  • Patent number: 10353452
    Abstract: A method for prioritized charging of battery backup units (BBUs) is provided. The method may include identifying critical system racks associated with computing data centers based on characteristics associated with the system racks on the computing data centers. The method may also include identifying critical system enclosures associated with the identified critical system racks based on system architectures associated with the computing data centers. The method may further include prioritizing the identified critical system enclosures based on parameters associated with the identified critical system enclosures. The method may also include identifying and ranking a plurality of critical BBUs associated with the identified and prioritized critical system enclosures based on prioritized charging rules associated with the plurality of critical BBUs. The method may further include charging the identified and ranked plurality of critical BBUs in an order based on the prioritized charging rules.
    Type: Grant
    Filed: January 27, 2017
    Date of Patent: July 16, 2019
    Assignee: International Business Machines Corporation
    Inventors: Ofir Elizov, Mudi M. Fluman, Igor Nabutovsky, Yehuda Shiran
  • Patent number: 10354044
    Abstract: A method of performing a resolution enhancement technique such as OPC on an initial layout description involves fragmenting a polygon that represents a feature to be created into a number of edge fragments. One or more of the edge fragments is assigned an initial simulation site at which the image intensity is calculated. Upon calculation of the image intensity, the position and/or number of initial simulation sites is varied. New calculations are made of the image intensity with the revised placement or number of simulation sites in order to calculate an OPC correction for the edge fragment. In other embodiments, fragmentation of a polygon is adjusted based on the image intensities calculated at the simulation sites. In one embodiment, the image intensity gradient vector calculated at the initial simulation sites is used to adjust the simulation sites and/or fragmentation of the polygon.
    Type: Grant
    Filed: June 7, 2017
    Date of Patent: July 16, 2019
    Assignee: Mentor Graphics Corporation
    Inventors: James Word, Nicolas B. Cobb, Patrick J. LaCour
  • Patent number: 10346581
    Abstract: A method for validating the design of an electronic circuit uses a static checker tool to verify the circuit design against rules and attributes of the components of the circuit. A power intent of the circuit, pins for power, ground and data signal inputs and outputs for each component, and a model for attributes and parameters of the pins are defined. The attributes of the components are defined in terms of input and output voltages; input and output currents; input and output voltage, current and data signal timing; and input and output voltage and current ranges and tolerances. A netlist of interconnections representing the designed circuit is validated against the power intent and the model for the attributes. A report is output describing the validity of the circuit based on the compatibility of the netlist, the power intent, and the model for the attributes of the components.
    Type: Grant
    Filed: September 13, 2017
    Date of Patent: July 9, 2019
    Assignee: Toshiba Memory Corporation
    Inventor: Benjamin Kerr
  • Patent number: 10346578
    Abstract: Systems and techniques for optimizing an integrated circuit (IC) design are described. Some embodiments can transform a circuit design into a logically-equivalent circuit design by: (1) creating a Wire-Length-Area Model (WLAM) for a portion of a first circuit design, (2) creating a second circuit design by replacing the portion of the first circuit design by the WLAM, (3) placing and routing the second circuit design to obtain a placed-and-routed second circuit design, and (4) creating a third circuit design that is logically-equivalent to the first circuit design based on the placed-and-routed second circuit design.
    Type: Grant
    Filed: November 1, 2017
    Date of Patent: July 9, 2019
    Assignee: Synopsys, Inc.
    Inventors: Jagat B. Patel, William Clark Naylor, Jr., Brent L. Gregory
  • Patent number: 10346572
    Abstract: A method of circuit design can include detecting, using a processor, a transactional inefficiency within trace data including transactions involving a first circuit block of a circuit design and, in response to the detecting, generating a modified version of the circuit design by including a transaction converter circuit block within the circuit design. The transaction converter circuit block can be coupled to the first circuit block and can be adapted to correct the transactional inefficiency.
    Type: Grant
    Filed: February 3, 2017
    Date of Patent: July 9, 2019
    Assignee: XILINX, INC.
    Inventors: Kyle Corbett, Khang K. Dao
  • Patent number: 10339615
    Abstract: The present invention is to provide an automatic IP core generation system that can reduce the loads on both an IP core vendor and a user. The present invention provides an automatic IP core generation system that generates an IP core in accordance with parameter information input from a user. The automatic IP core generation system includes: a parameter acquisition unit that acquires the parameter information; a meta IP core information storage unit that stores a meta IP core model as a model for generating various IP cores; a component library information storage unit that stores a component to be used in the IP core and the meta IP core model; an IP core generation unit that generates a package containing the IP core in accordance with the parameter information; and a package output unit that outputs the package.
    Type: Grant
    Filed: January 18, 2016
    Date of Patent: July 2, 2019
    Assignees: PROFOUND DESIGN TECHNOLOGY CO., LTD.
    Inventors: Makoto Hayashi, Yasutaka Tsukamoto
  • Patent number: 10336198
    Abstract: A charge cable lock device is for use with an inlet that includes an inlet housing. A charge cable including a rocking arm with a hooking portion is connected in a removable manner to the inlet. The charge cable lock device includes a lock member, a lock housing, and a fixing pin. The lock member is movable to a lock position and an unlock position and configured to contact the rocking arm to restrict disengagement of the hooking portion of the rocking arm from the inlet when the lock member is located at the lock position. The lock housing supports the lock member. The fixing pin is configured to be inserted into the lock housing and the inlet housing and fix the lock housing to the inlet traversing the lock housing and the inlet housing.
    Type: Grant
    Filed: May 25, 2017
    Date of Patent: July 2, 2019
    Assignee: KABUSHIKI KAISHA TOKAI RIKA DENKI SEISAKUSHO
    Inventors: Takahiro Hirashita, Keiji Kahara, Hiroshi Aoyama, Eiji Kitano, Masaru Sasaki
  • Patent number: 10340714
    Abstract: The present disclosure discloses a system and method of adjusting an output parameter of a secondary battery. The system according to the present disclosure determines a voltage, a current, and a temperature of the secondary battery, determines a state of charge of the secondary battery using the current, determines a deration target current value calculated from a maximum value of a predefined resistance change rate, which corresponds to the state of charge and the temperature, and an output maintaining time, when the voltage of the secondary battery decreases to a preset threshold voltage or lower, and provides an output parameter including at least one of the deration target current value and a deration target output value determined therefrom to a control system of a load device supplied with power from the secondary battery.
    Type: Grant
    Filed: November 14, 2016
    Date of Patent: July 2, 2019
    Assignee: LG CHEM, LTD.
    Inventors: Sun-Young Cha, Won-Tae Joe
  • Patent number: 10338888
    Abstract: An electronic component footprint setup system in collaboration with a circuit layout system and a method thereof are provided in the present disclosure. The electronic component footprint setup system in collaboration with a circuit layout system provides a user operating the circuit layout system with an interface on which parameters of an electronic component footprint to be created are configured; the parameters of the electronic component footprint are transformed for conforming to electronic component footprint specifications used in the circuit layout system; characteristic values of the electronic component footprint are calculated according to electronic component footprint specifications and electronic component footprint setup regulations; the electronic component footprint is created in the circuit layout system according to the characteristic values.
    Type: Grant
    Filed: August 8, 2017
    Date of Patent: July 2, 2019
    Assignee: Footprintku Inc.
    Inventors: Cheng-Ta Lu, Yu-Cheng Hu, Guan-Yu Shih, Kun-You Lin, Mong-Fong Horng
  • Patent number: 10339263
    Abstract: An electronic component footprint verification system and a method thereof are provided in the present disclosure. The system is available to an external user for selecting an electronic component footprint to be verified, reading a verification rule checklist in an external database, extracting characteristics of the electronic component footprint, accessing characteristic data from the electronic component footprint, verifying the characteristic data based on the verification rule checklist, and displaying a verification result.
    Type: Grant
    Filed: August 8, 2017
    Date of Patent: July 2, 2019
    Assignee: Footprintku Inc.
    Inventors: Yu-Siang Fan Jiang, Mong-Fong Fan Horng, Yan-Jhih Wang, Jun-Qiang Wei, Yi-Ting Chen
  • Patent number: 10332663
    Abstract: A coil module includes a substrate; a wireless charging coil formed in a substantially central portion of the substrate positioned on both surfaces of the substrate; and a first wireless communications coil which does not directly contact the wireless charging coil and is formed in the substantially central portion of the substrate on both surfaces of the substrate, wherein, in a region of the substrate in which the wireless charging coil and the first wireless communications coil are overlapped with each other, the wireless charging coil is formed on one surface of the region and the first wireless communications coil is formed on the other surface of the region, respectively.
    Type: Grant
    Filed: January 31, 2017
    Date of Patent: June 25, 2019
    Assignee: Samsung Electro-Mechanics Co., Ltd.
    Inventors: Hyung Wook Cho, Si Hyung Kim, Sung Heum Park, Hee Seung Kim, Ki Won Chang, Jae Suk Sung, Chang Mok Han
  • Patent number: 10331847
    Abstract: An automated electronic component footprint setup system and a method thereof are provided in the present disclosure. The system is available to not only an external first user for configuring characteristic parameters of an electronic component for the database but also an external second user for configuring setup parameters of an electronic component footprint to be created. Then, the system is to create an electronic component footprint of a specific electronic layout system according to the characteristic parameters of the electronic component, component setup regulations and the setup parameters, all of which correspond to the electronic component footprint.
    Type: Grant
    Filed: August 8, 2017
    Date of Patent: June 25, 2019
    Assignee: FOOTPRINTKU INC.
    Inventors: Cheng-Ta Lu, Yu-Siang Fan Jiang, Jiun-Huei Ho, Chun-Chieh Tsai, Yi-Ting Chen