Patents Examined by Paul Dinh
  • Patent number: 11027621
    Abstract: An ECU performs a first process of transmitting first information to a server, and performs a second process by acquiring second information from the server. The first information includes temperature information about a temperature of an inlet during external charging, and information for identifying a charging station connected to the inlet. The second process includes a process of controlling the external charging based on the second information acquired before a start of the external charging. The second information includes abnormal overheat information about the charging station connected to the inlet. The occurrence of abnormal overheat is determined based on the temperature of the inlet during the external charging.
    Type: Grant
    Filed: March 29, 2019
    Date of Patent: June 8, 2021
    Assignee: TOYOTA JIDOSHA KABUSHIKI KAISHA
    Inventor: Shigeki Kinomura
  • Patent number: 11030378
    Abstract: Various embodiments described herein provide for track assignment of wires of a network of a circuit design by dynamic programming. In particular, various embodiments use a dynamic programming process to determine a set of breaking points for a routing wire of a global-routed and layer-assigned circuit design, and to determine track assignments for each of the sub-wires (sub-routes) formed by applying the set of selected breaking points to the routing wire. This results in a set of track-assigned sub-wires (or track-assigned sub-routes), which various embodiments can connect together to generate a connected set of track-assigned sub-wires that can be used in place of the routing wire.
    Type: Grant
    Filed: June 17, 2020
    Date of Patent: June 8, 2021
    Assignee: Cadence Design Systems, Inc.
    Inventors: Yi-Xiao Ding, Mehmet Can Yildiz, Zhuo Li
  • Patent number: 11031793
    Abstract: A battery and a method for operating a battery, in particular for a motor vehicle, including multiple battery cells, which have respective battery cell housings with electric terminals via which the battery cells are electrically interconnected, wherein a respective cell branch connecting the terminals and having a galvanic cell is arranged in the battery cell housings, a respective bypass branch for bypassing the respective galvanic cell is arranged in the battery cell housings; each cell branch has a first switching element for opening and closing the cell branch, and each bypass branch has a second switching element for opening and closing the bypass branch.
    Type: Grant
    Filed: March 14, 2019
    Date of Patent: June 8, 2021
    Assignee: AUDI AG
    Inventors: Michael Hinterberger, Berthold Hellenthal
  • Patent number: 11023636
    Abstract: Disclosed are methods, systems, and articles of manufacture for characterizing an electronic design with a susceptibility window. These techniques identify a set of multiple aggressors in an electronic design and determine, at a susceptibility window module stored in memory and executing in conjunction with a microprocessor of a computing node, a susceptibility window for an internal node of a victim and a timing window for the set of multiple aggressors in the electronic design. These techniques further determine a subset having at least one aggressor using at least the susceptibility window of the victim and the timing window for the set of multiple aggressors, and determine whether a glitch in the electronic design causes a violation at the internal node of the electronic design based at least in part upon the timing window and the susceptibility.
    Type: Grant
    Filed: May 13, 2020
    Date of Patent: June 1, 2021
    Assignee: Cadence Design Systems, Inc.
    Inventors: Igor Keller, Ratnakar Goyal, Manuj Verma, Harmandeep Singh
  • Patent number: 11023640
    Abstract: Disclosed are methods, systems, and articles of manufacture for characterizing timing behavior of an electronic design with a derived current waveform. A set of inputs is determined from a set of electrical characteristics of an electronic design or a portion thereof. Moreover, A derived current waveform is determined at one or more modules stored in memory and executing in conjunction with a microprocessor of a computing node based at least in part upon the set of inputs. The electronic design or the portion thereof is characterized based at least in part upon the derived current waveform.
    Type: Grant
    Filed: May 13, 2020
    Date of Patent: June 1, 2021
    Assignee: Cadence Design Systems, Inc.
    Inventors: Igor Keller, Chirayu S. Amin, Omid Assare
  • Patent number: 11017146
    Abstract: An integrated circuit includes a first set of devices, a set of metal layers and a header circuit. The first set of devices are configured to operate on a first supply voltage, and are located on a first layer of the integrated circuit. The set of metal layers are above the first layer, and includes a first metal layer and a second metal layer. The first metal layer extends in at least a first direction and a second direction. The header circuit is above the first set of devices. At least a portion of the header circuit is positioned between the first metal layer and the second metal layer. The header circuit is configured to provide the first supply voltage to the first set of devices, and is configured to be coupled to a second voltage supply having a second supply voltage different from the first supply voltage.
    Type: Grant
    Filed: July 2, 2019
    Date of Patent: May 25, 2021
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: John Lin, Chung-Hsing Wang, Chin-Shen Lin, Kuo-Nan Yang
  • Patent number: 11018532
    Abstract: A wireless power charger (WPC) integrated into a charging pad (CP) includes a wireless power transmitter (WPT), a location sense mechanism (LSM), a transport mechanism (TM) and a Central Control Unit (CCU). The LSM discovers and conveys the position of a portable device to the CCU when the device is placed on the CP to have its battery wirelessly charged. The LSM uses RF signaling and other capabilities in wireless connectivity standards to detect location of device. With information from the LSM, the CCU, via the TM, moves the WPTM in close proximity to the device. Once at the device position, the WPTM senses the location of the receiver coil in the device, adjusts its position via the TM to gain strong alignment and provides power wirelessly. When charging is complete or if the device is removed from the charging pad, the WPTM returns to its home-base location.
    Type: Grant
    Filed: February 24, 2019
    Date of Patent: May 25, 2021
    Assignee: WIPQTUS INC.
    Inventor: Ganapathy Sankar
  • Patent number: 11003826
    Abstract: Strategies are stored in a memory arrangement, and each strategy includes a set of parameter settings for a design tool. The design tool identifies a set of features of an input circuit design and applies classification models to the input circuit design. Each classification model indicates one the strategies, and application of each classification model indicates a likelihood that use of the strategy would improve a metric of the input circuit design based on the set of features of the input circuit design. One strategy of the plurality of strategies is selected based on the likelihood that use of the one strategy would improve the metric of the input circuit design, and the design tool is configured with the set of parameter settings of the one strategy. The design tool then processes the input circuit design into implementation data that is suitable for making an integrated circuit (IC).
    Type: Grant
    Filed: April 29, 2019
    Date of Patent: May 11, 2021
    Assignee: XILINX, INC.
    Inventors: Srinivasan Dasasathyan, Padmini Gopalakrishnan, Vishal Tripathy, Vikas N. Vedamurthy, Sumit Nagpal
  • Patent number: 10997354
    Abstract: In a first integrated circuit column, a first cell active area top edge is separated by a first separation distance from a first barrier line, a first cell active area bottom edge is separated by a second separation distance from a second barrier line, a second cell active area top edge is separated by the second separation distance from a third barrier line, and a second active area bottom edge is separated by the first separation distance from a fourth barrier line. In a second column a third cell active area top edge is separated from a fifth barrier line by the first distance, and a third cell active area bottom edge is separated from a sixth barrier line by a third distance. The first and third separation distances are different from the second separation distance. The first barrier line aligns with the fifth barrier line.
    Type: Grant
    Filed: December 13, 2018
    Date of Patent: May 4, 2021
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Yu-Tao Yang, Wen-Shen Chou, Yung-Chow Peng
  • Patent number: 10984159
    Abstract: A method, and apparatus and a computer program product for determining coverage in hardware verification based on relations between coverage events. The method comprises generating an over-approximation model of the hardware being verified to perform formal verification thereof with respect to a target coverage event being utilized in the verification process along with a set of coverage events. A score indicating an estimated conditional probability to hit the target coverage event in the verification process, given that the coverage event is hit in the verification process, may be determined for each coverage event based on the formal verification. The method further comprises selecting test suits to be executed in the verification process based on the scores and the test suits probability to hit each coverage event. The verification process may be the performed the selected test suits in order to cover the target coverage event.
    Type: Grant
    Filed: May 10, 2020
    Date of Patent: April 20, 2021
    Assignee: International Business Machines Corporation
    Inventors: Ziv Nevo, Alexander Ivrii, Avi Ziv, Raviv Gal, Haim Kermany
  • Patent number: 10984160
    Abstract: Circuit analysis and modification by receiving a first description of a circuit, the first description having a first level of detail, receiving a second description of the circuit, the second description having a second level of detail, performing a circuit simulation according to the first description, identifying an active node of the first description according to the simulation, and modifying the second description according to the active node.
    Type: Grant
    Filed: May 7, 2020
    Date of Patent: April 20, 2021
    Assignee: International Business Machines Corporation
    Inventors: Martin Bernhard Schmidt, Alexander Fritsch, Werner Juchmes, Simon Brandl
  • Patent number: 10977407
    Abstract: An integrated circuit includes an intellectual property (IP) block including a plurality of standard cells. A first power gating cell supplies power to the IP block via a first power rail extending in a first horizontal direction. A first conductive line extends in a second horizontal direction perpendicular to the first horizontal direction in a first metal layer. A second power gating cell is arranged adjacent to the first power gating cell in the second horizontal direction to supply power to the IP block via a second power rail extending in the first horizontal direction. A second conductive line extends in the second horizontal direction in the first metal layer. The first conductive line is coupled with the second conductive line in the second horizontal direction.
    Type: Grant
    Filed: September 5, 2019
    Date of Patent: April 13, 2021
    Assignee: Samsung Electronics Co., Ltd.
    Inventor: Hoijin Lee
  • Patent number: 10970438
    Abstract: A method of generating a layout diagram of an IC device includes assigning a leakage constraint to a first schematic net of the IC device and determining a violation of the leakage constraint based on a dummy gate region. The IC layout diagram includes the dummy gate region between a first component of the first schematic net and a second component of a second schematic net of the IC device. The method includes modifying the IC layout diagram in response to the leakage constraint violation, and generating a layout file based on the modified IC layout diagram.
    Type: Grant
    Filed: July 1, 2019
    Date of Patent: April 6, 2021
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.
    Inventor: Tien-Chien Huang
  • Patent number: 10963619
    Abstract: A method of designing a memory system, which includes a semiconductor device and a power supply circuit supplying power to the semiconductor device via a board power distribution network, includes analyzing power characteristics of respective components of the power supply circuit by using a power characteristic model of the power supply circuit, and analyzing power characteristics of the memory system. The power characteristic model of the power supply circuit includes an encrypted model.
    Type: Grant
    Filed: October 7, 2019
    Date of Patent: March 30, 2021
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Kun Joo, Jaeyoung Shin
  • Patent number: 10963615
    Abstract: Some examples described herein relate to routing in routing elements. In an example, a design system includes a processor and a memory, storing instruction code, coupled to the processor. The processor is configured to execute the instruction code to model a communication network comprising switches interconnected in an array of data processing engines (DPEs), generate global routes of nets in the modeled communication network, generate detailed routes of the nets using the global routes, and translate the detailed routes to a file. Each of the switches has multiple input or output channels connected to another switch that are modeled as a single input or output edge, respectively, connected to the other switch. Each global route is generated through edge(s) of the switches. Each detailed route is generated comprising identifying one of the multiple input or output channels modeled by each edge through which the respective global route is generated.
    Type: Grant
    Filed: April 30, 2019
    Date of Patent: March 30, 2021
    Assignee: XILINX, INC.
    Inventors: Abhishek Joshi, Grigor S. Gasparyan
  • Patent number: 10956639
    Abstract: A method of time budgeting an integrated circuit (IC) that includes determining an initial value of time delay variables for each block of a plurality of blocks along a set of timing paths based on delays of each design module of the blocks and determining a value of at least one advanced timing factor adjusting a clock period of the IC along each timing path. The method then generates a time budget for ports along each timing path based on the value of the at least one advanced timing factor and the initial value of the time delay variable. The method then optimizes the value of time delay variables by calculating new values of the time delay variables that satisfy each timing path to minimize a possibility of timing violations and to satisfy the clock period of the IC, which is adjusted by the value of the advanced timing factor.
    Type: Grant
    Filed: December 31, 2019
    Date of Patent: March 23, 2021
    Assignees: ARCADIA INNOVATION INCORPORATED, HYGON INFORMATION TECHNOLOGY CO., LTD.
    Inventors: Yizhou Lin, Jian Tang, Hongchang Liang
  • Patent number: 10958092
    Abstract: A semiconductor integrated circuit may include a recharge switch and a Wireless Recharge/MST unit. The recharge switch is connected with a battery through an intermediate node and provides a current path for wirely charging the battery in a wired charging mode. The Wireless Recharge/MST unit is connected between the intermediate node and a ground. The Wireless Recharge/MST unit disconnects the intermediate node and the ground in the wired charging mode, provides a wireless charging current to the battery through the intermediate node in a wireless charging mode, and is supplied with a current for generating a magnetic signal from the battery through the intermediate node in a magnetic secure transmission (MST) mode.
    Type: Grant
    Filed: October 28, 2019
    Date of Patent: March 23, 2021
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Sungwoo Lee, Hyoungseok Oh, Kwang Chan Lee
  • Patent number: 10956648
    Abstract: Systems and methods for designing a dummy pattern layout for improving surface flatness of a wafer are provided. An exemplary system includes at least one processor and at least one memory storing instructions. The instructions, when executed by the at least one processor, cause the at least one processor to perform operations. The operations include identifying a feature pattern corresponding to a functional region of the wafer. The operations also include determining a property of the feature pattern based on a script associated with the feature pattern. The operations further include determining a dummy pattern rule based on the property of the feature pattern. Moreover, the operations include generating a dummy pattern corresponding to a vacant region of the wafer by wrap-filling dummy units in an adjacent area surrounding the feature pattern based on the dummy pattern rule.
    Type: Grant
    Filed: March 8, 2019
    Date of Patent: March 23, 2021
    Assignee: YANGTZE MEMORY TECHNOLOGIES CO., LTD.
    Inventor: Bi Feng Li
  • Patent number: 10957417
    Abstract: Systems, apparatuses, and methods for on-die memory power analytics and management are described. In some examples, the memory analytics and management may include a frequency-dependent analysis or simulation model of a memory die to determine an operating characteristic of the die. A set of ports of the memory die may be selected and one or more alternating current (AC) excitation signals may be applied to the ports to determine an impedance associated with the ports. The impedance may be used to determine one or more parameters (e.g., scattering, impedance) to analyze a die and for subsequently managing power distribution on the die. Analytics on a subset of ports on a die may be used to simulate the electrical response of the entire memory die and thus manage power delivery for the die.
    Type: Grant
    Filed: February 10, 2020
    Date of Patent: March 23, 2021
    Assignee: Micron Technology, Inc.
    Inventors: Fuad Badrieh, Thomas H. Kinsley, Baekkyu Choi
  • Patent number: 10949592
    Abstract: Example implementations described herein are directed to resolving issues related to the processor model in the S-PILS (Simulated Processor In the Loop Simulation) system, such as processor model correctness and simulation execution speed, by using the actual Central Processing Unit (CPU) board with silicon CPU instead of the virtual SoC model in the S-PILS.
    Type: Grant
    Filed: March 23, 2020
    Date of Patent: March 16, 2021
    Assignee: HITACHI AUTOMOTIVE SYSTEMS, LTD.
    Inventor: Ichiki Homma