Abstract: A system, method and a computer program product for processing media content on a media player having direct access to hardware are provided in exemplary embodiments. When the media player is initialized, an operating system is placed into a stand-by mode that decreases power consumption on an electronic device. Instead of the operating system, a hardware pipeline processes media content. A hardware pipeline is dedicated to process a media content based on the media content type. The media content is processed using the dedicated hardware pipeline to reduce the power consumption during processing.

Abstract: Processor power may be managed by executing state storage and power gating instructions after receiving an idle indication. The idle indication may be received while the processor is executing instructions in a first mode, and the processor may execute the state storage and power gating instructions in a second mode. The state storage and power gating instructions may be inaccessible to the processor when operating in the first mode.

Abstract: A method and system for optimizing a core voltage level of a portable computing device (“PCD”) and enhancing frequency performance of individual subcomponents are disclosed. A plurality of voltage values for a plurality of subsystems is determined. At least one subsystem is a multiplexed subsystem. Next, a reduced set of voltage values is calculated based on the plurality of voltage values and an optimized voltage level is determined for a shared power domain. The shared power domain is subsequently set to the optimized voltage level. If the optimized voltage level is determined to exceed a required voltage level for the at least one multiplexed subsystem when it is running the plurality of processing engines, a subset of the plurality of processing engines may be identified to process a workload of the multiplexed system at a more efficient level of power consumption than the full plurality of processing engines.

Abstract: A computer system includes a display, a motherboard and a power circuit. The display includes a video interface. The motherboard includes a super input-output (SIO) chip. The power circuit includes a first switch unit, a second switch unit, a third switch unit, and an oscillator. When the display is powered on, the video interface outputs a high level signal, the first switch unit is turned on, a power supply powers the oscillator through the first switch unit. The oscillator operates and outputs a high level signal, the second switch unit is turned on, a power-on signal pin of the SIO chip receives a low level signal, and the motherboard is turned on.

Abstract: An embodiment is a circuit including a main power supply coupled to a first node, a charge reservoir coupled between a second node and ground, an isolation circuit coupled between the first node and the second node, and a plurality of secondary power supplies coupled to the second node, the plurality of secondary power supplies configured to receive power from the main power supply. The circuit further includes a detector circuit coupled to the first node, the detector circuit configured to detect the presence and absence of a first supply voltage at the first node, and a timing circuit coupled between the detector circuit and the plurality of secondary power supplies, the timing circuit configured to enable and disable the plurality of secondary power supplies in predetermined sequences based on the detection of the first supply voltage by the detector circuit.

Abstract: A power control system and a power control method thereof applied to a computer device are provided. The computer device includes a computer system and a power system. The power system includes a plurality of voltage regulators for providing supply voltages to the components of the computer device. The power control system is coupled to the computer system and the power system and includes an overclocking frequency mode. When the computer system receives an OFF signal and enters a non-operating mode, and when the power control system is in the overclocking frequency mode, the power control system sends a SYSTEM-SHUTDOWN signal to the computer system to control the power system to enter the non-operating mode and to control the power system to keep outputting supply voltages.

Abstract: Hybrid threading in a processor is described. An integrated circuit that implements hybrid threading includes a power control unit (PCU), a first functional hardware unit coupled to the PCU, and a second functional hardware unit coupled to the PCU. The first functional hardware unit and the second functional hardware unit are heterogeneous functional hardware units. The PCU is configured to monitor at least one power attribute of the first and second functional hardware units. The PCU is further configured to calculate an aggregate power value based on the monitored at least one power attribute. Upon determining that the aggregate power value is below a power threshold, the PCU is also configured to calculate a first frequency for the first functional hardware unit and a second frequency for the second functional hardware unit that results in an updated aggregate power value that is closer to the power threshold.

Abstract: Methods, apparatuses and storage medium associated with providing firmware to a device are disclosed herein. In various embodiments, an apparatus may include a device, and a processor to host a computing environment that includes the device and a device driver of the device. Further, the apparatus may include a firmware agent, disposed outside the computing environment, to provide, on behalf of the device driver, firmware to the device on power-on of the device. Other embodiments may be described and claimed.

Abstract: Techniques are described for facilitating execution of software programs in a configurable manner, including to configure bootstrapping operations that are performed at startup of the software programs. At least some of the software programs may be software images that each include, for example, a defined file system, an operating system, and one or more application programs. In addition, configuration of the software programs' startup may include using distinct bootstrap packages that each include their own distinct file system, such that loading of a bootstrap package within a software image includes adding the included file system of the bootstrap package to a new location within the defined file system of the software image (e.g., by mounting the included file system of the bootstrap package within the defined file system of the software image, and optionally removing the included file system of the bootstrap package after bootstrapping operations are completed).

Abstract: The setting in a configuration register is controlled based on a value stored in a management register and/or based on generation of a reset signal during a debugging operation or detection of a malfunction or power state transition in an electronic system. The management register may allocate a single bit to each configuration register, and the setting to be loaded into the configuration register is to be controlled based on the value of the bit. Additionally, or alternatively, the setting in the configuration register may be controlled when the reset signal assumes a value indicating that a default setting is to be stored.

Abstract: A low standby power DC-DC converter can be powered down during standby mode. The DC-DC converter can be periodically awakened between sleep cycles to check if the output voltage needs to be recharged (refreshed). The duration of the sleep cycles can be varied to accommodate for changing load conditions that would affect the output voltage.

Abstract: A control method and an electronic device using the control method are described. The control method includes, when the processing unit is in a first state, the communicating unit receives current network data; the communicating unit determines whether a communication state of the network data satisfies a predetermined condition; if the communication state does not satisfy the predetermined condition, then the communicating unit stores the current network data into a cache module of the communicating unit; and if the communication state satisfies the predetermined condition, then the communicating unit transmits the current network data to the processing unit, so that the processing unit changes from the first state to a second state, wherein power consumption in the first state is lower than that in the second state.

Abstract: Monitoring is performed for a requested change in a number of active processor cores within a multi-core processor. A current power level setting of the multi-core processor is checked based on the requested change in the number of active processor cores. A targeted power level setting associated with the requested change in the number of active processor cores is determined, where the targeted power level setting incorporates a worst case noise level margin defined on an active processor core basis. The current power level setting is adjusted to align with the targeted power level based on determining that the current power level setting fails to meet the targeted power level within a threshold band.

Abstract: Embodiments relate to controlling a temperature of a solid state memory device using queue depth management by monitoring an operating temperature of each of a plurality of solid state drives of the solid state memory device. Based on a determination that the operating temperature of one of the plurality of solid state drives exceeds local device threshold values, the method includes receiving an indication that one or more local measures have been taken by the solid state memory device. Based on a determination that the operating temperature of one of the plurality of solid state drives exceeds a secondary global threshold value, the method includes reducing a queue length for the solid state memory device.

Abstract: An information processing system includes an operation part that receives an operation performed by a user; and a body part that operates based on a request from the operation part. The operation part includes a power control part that, when receiving a power turning off instruction from the body part, reboots the operation part and causes the operation part to stand by in a power saving state in which some of operations are stopped, and, when receiving a start up notification from the body part, causes the operation part to return from the power saving state.

Abstract: This document discloses a solution for employing a power-save mode in an electronic device providing, in a display unit, a plurality of home screens and a mechanism to switch from one home screen to another home screen in response to a user input received through user input means of the electronic device. At least one of the home screens is a home screen for a power-save mode of the electronic apparatus and, upon detecting a user input causing a switch to the home screen for the power-save mode, the electronic device switches on at least some of the power-save features of the electronic device.

Abstract: Latency-based power mode units for controlling power modes of processor cores, and related methods and systems are disclosed. In one aspect, the power mode units are configured to reduce power provided to the processor core when the processor core has one or more threads in pending status and no threads in active status. An operand of an instruction being processed by a thread may be data in memory located outside processor core. If the processor core does not require as much power to operate while a thread waits for a request from outside the processor core, the power consumed by the processor core can be reduced during these waiting periods. Power can be conserved in the processor core even when threads are being processed if the only threads being processed are in pending status, and can reduce the overall power consumption in the processor core and its corresponding CPU.

Abstract: A program startup method, apparatus and terminal are provided. The method includes: determining at least one target program from programs according to history startup information of the plurality of programs in a prefetch database, where the history startup information comprises startup moments of the plurality of programs; loading prefetch data corresponding to the target program into internal memory and locking the prefetch data in startup of an automatic startup item of an operating system; unlocking the prefetch data corresponding to the target program in the case where a startup event of the target program is detected; accessing the prefetch data corresponding to the target program in the internal memory; and running code of the target program according to the prefetch data corresponding to the target program to start up the target program.

Abstract: In one embodiment, individual or groups of heat generating data processing operations are rate-controlled such that a component, a set of components, a board or line card, and/or an entire apparatus or any portion thereof stays within a corresponding heat budget. One or more heat price tags are associated with these data processing operations which are used to determine whether or not a corresponding data processing operation can be currently performed within one or more corresponding heat budgets. If so, the data procession operation proceeds. If not, the data processing operation is delayed. Examples of such data processing operations include, but are not limited to, data retrieval from memory, data storage in memory, lookup operations in memory, lookup operations in a binary or ternary content-addressable memory, regular expression processing, cryptographic processing, or data manipulation.

Abstract: Particular embodiments described herein can offer a method for managing power for at least one processor that includes evaluating a plurality of ports associated with an electronic device; determining that a particular pin associated with at least one of the ports is not receiving a signal; disabling a squelch function associated with the electronic device; and gating power associated with a physical layer (PHY) of the electronic device.