Patents Examined by Paul L Rodriguez
  • Patent number: 8019574
    Abstract: A required payload volume of a Blended Wing Body air vehicle is determined and analyzed for a list of corner points that is passed to a Loft Module as keep-out points to be enclosed by a body portion established using a faceted minimum volume. Trapezoidal wing shape and size are determined, a leading edge of the body portion and trapezoidal wing leading edge are trimmed and a trailing edge of the body portion and trapezoidal wing trailing edge are blended. A leading edge elevation is established and with leading edge radius as an input smoothly encloses the payload volume in a first set of defined aerodynamic sections. A second set of aerodynamic sections and transition sections between the body portion and the trapezoidal wing are defined. The blended wing body is then lofted based on the defined sections.
    Type: Grant
    Filed: December 17, 2007
    Date of Patent: September 13, 2011
    Assignee: The Boeing Company
    Inventors: Thomas Allen Hogan, Christopher K. Droney, Dino Roman
  • Patent number: 8010334
    Abstract: A test system or simulator includes an integrated circuit (IC) benchmark software program that executes workload program software on a semiconductor die IC design model. The benchmark software program includes trace, simulation point, basic block vector (BBV) generation, cycles per instruction (CPI) error, clustering and other programs. The test system also includes CPI stack program software that generates CPI stack data that includes microarchitecture dependent information for each instruction interval of workload program software. The CPI stack data may also include an overall analysis of CPI data for the entire workload program. IC designers may utilize the benchmark software and CPI stack program to develop a reduced representative workload program that includes CPI data as well as microarchitecture dependent information.
    Type: Grant
    Filed: April 30, 2008
    Date of Patent: August 30, 2011
    Assignee: International Business Machines Corporation
    Inventors: Robert H Bell, Thomas W Chen, Jr., Venkat R Indukuru, Alex E Mericas, Pattabi M Seshadri, Madhavi G Valluri
  • Patent number: 8010330
    Abstract: The space including a particle system is discretized into volume elements. Signed distance values at each time and velocity values at a time are assigned to volume elements based on the particle system. The each volume element's position at the current time is extrapolated to an additional position at each additional time based on its respective velocity value. A temporally coherent signed distance value for each volume element is determined from its signed distance value and the signed distance values at the associated additional position at each additional time. A surface extracted from the temporally coherent signed distance values will be temporally coherent over the interval including the current time and the one or more additional times. Arbitrary surface properties may also be associated with volume elements and temporally coherent surface property values may be determined for each volume element using its respective velocity value in a similar manner.
    Type: Grant
    Filed: March 7, 2008
    Date of Patent: August 30, 2011
    Assignee: Pixar
    Inventors: Chen Shen, Apurva Shah
  • Patent number: 8010336
    Abstract: A method for simulating the configuration of an electrical power network for robust power restoration method is described. The method involves analyzing an electrical network topology in respect of electrical power sources, electrical bridges and other associated data, such as safety data, loss data, etc. The method determining a set of virtual paths within a mesh electrical power network, the network having a plurality of sources of electrical power. Each of the virtual paths allowing determination of suitable locations for provisioning at least a non-conducting electrical bridge. The method allowing the state of the electrical bridges to be modified to restore power when a fault is detected within the electrical power network.
    Type: Grant
    Filed: November 8, 2007
    Date of Patent: August 30, 2011
    Assignee: Virelec Ltd.
    Inventor: Eduardo Chaiquin
  • Patent number: 8005659
    Abstract: A simulator for simulating a first object and a second object that is coupled to the first object is disclosed. The simulator models the first and second objects as a plurality of segments, with each segment having a plurality of nodes connected by one or more edges. The simulator then indexes each of the nodes and couples at least one node of the first object to a node of the second object. The indexing and coupling is based on the current simulated position of the first and second objects. The simulator then generates and solves a linear system of equations Ay=b from the indexing, and updates a position of each of the nodes. The simulator flow then dynamically re-indexes the nodes, and continues in a loop.
    Type: Grant
    Filed: July 6, 2007
    Date of Patent: August 23, 2011
    Assignee: Immersion Medical, Inc.
    Inventors: Donald Nelson, Milan Ikits
  • Patent number: 8005653
    Abstract: A modeller for a system for determining a residual error probability. The modeller includes a component modeller, which is adapted to receive an error probability and to model a change of the error probability due to a behaviour of a system component, in order to output a changed error probability as residual error probability.
    Type: Grant
    Filed: March 27, 2007
    Date of Patent: August 23, 2011
    Assignee: Infineon Technologies AG
    Inventor: Stefan Rüping
  • Patent number: 8005650
    Abstract: Embodiments of the invention include a method for generating a two-dimensional (2D) flattened nailboard representation of a wiring harness in a three-dimensional (3D) computer-aided design (CAD) model. The nailboard representation invention may be used to provide a dimensionally accurate “flattened” view of a complex 3D wiring harness depicted in a CAD model, without cutting any of the wires included in the harness, and minimizing the overlap of multiple exposed wires present in wire loops.
    Type: Grant
    Filed: February 28, 2008
    Date of Patent: August 23, 2011
    Assignee: Autodesk, Inc.
    Inventors: Steve Flores, Baolin Jiang, Wang Xianfeng, Chengyun Yang
  • Patent number: 8005660
    Abstract: An Integrated Circuit Design tool incorporating a Stochastic Analysis Process (“SAP”) is described. The SAP can be applied on many levels of circuit components including transistor devices, logic gate devices, and System-on-Chip or chip designs. The SAP replaces the large number of traditional Monte Carlo simulations with operations using a small number of sampling points or corners. The SAP is a hierarchical approach using a model fitting process to generate a model that can be used with any number of performance metrics to generate performance variation predictions along with corresponding statistical information (e.g., mean, three-sigma probability, etc.). A hierarchical SAP process breaks an overall circuit into a plurality of subcircuits and performs circuit simulation and SAP analysis steps on each subcircuit. An integration and reduction process combines the analysis results of each subcircuit, and a final SPICE/SAP process provides a model for the overall circuit based on the subcircuits.
    Type: Grant
    Filed: June 27, 2007
    Date of Patent: August 23, 2011
    Assignee: Anova Solutions, Inc.
    Inventors: Hsien-Yen Chiu, Meiling Wang, Jun Li
  • Patent number: 8005553
    Abstract: A method or apparatus automatically configures a control module for synchronous execution on a Fieldbus segment of a process control network by determining if all of the critical function blocks of a particular control module can be assigned to FOUNDATION® Fieldbus field devices or to the I/O device associated with a particular Fieldbus segment. If so, the method or apparatus automatically assigns the function blocks of the control module, which would otherwise be scheduled to execute in a controller, to the I/O device for the Fieldbus segment. This technique enables all of the critical or necessary function blocks within the control module to execute in one macrocycle of the Fieldbus segment, thereby executing synchronously on a Fieldbus segment.
    Type: Grant
    Filed: December 31, 2007
    Date of Patent: August 23, 2011
    Assignee: Fisher-Rosemount Systems, Inc.
    Inventors: Alper T. Enver, Kenneth D. Krivoshein, Daniel D. Christensen, Ram Ramachandran, John M. Lucas, Ebtesam S. Tanyous
  • Patent number: 8000942
    Abstract: This disclosure relates to a design methodology used in manufacturing a broaching tool for cutting slots in aerospace disk applications. The method includes modeling geometry of the slot and the broach tool, which is based upon an initial minimum tooth rise that is determined empirically for the particular disk material. The number of broach inserts and teeth per insert is calculated, and the broach inserts are modeled. The stresses and deformation of the lug are calculated in a finite elements environment based upon simulated incremental broach tool movements. If the lug is not within specifications based upon design constraints, then the broach tool is revised and the simulations are repeated until the slot is within the desired specifications.
    Type: Grant
    Filed: May 14, 2008
    Date of Patent: August 16, 2011
    Assignee: United Technologies Corporation
    Inventors: Tahany Ibrahim El-Wardany, Shaoluo L. Butler, Barclay Bingham Young, Jr., Agnieszka M. Wusatowska-Samek, James D. Campbell, Jr., Jason Elliott, Adam Cade Wilcox, Ryan Clifford Cox
  • Patent number: 8000950
    Abstract: Latches in a net of a simulated integrated circuit design are initialized to known logical states prior to application of a reset signal at the beginning of the simulation. The logical states may be set by generating a list of the latches, sorting them in random order, and then dividing them into two groups based on the random order with high and low logical states respectively assigned to the two groups. In a specific implementation the latch states are set using an HDL force command prior to applying the reset signal, and the force command is removed after applying the reset signal using an HDL release command. If the circuit description is a gate-level netlist, then logical states of gates within the storage elements are also set.
    Type: Grant
    Filed: July 15, 2008
    Date of Patent: August 16, 2011
    Assignee: International Business Machines Corporation
    Inventors: Kalpesh Hira, Neil A. Panchal
  • Patent number: 8000951
    Abstract: A timing analysis apparatus has a block simulation information storing section, a SPICE deck generating section, and a feedback-based static timing analyzing section. The block simulation information storing section stores simulation information for each block when performing circuit analysis by partitioning a circuit into blocks, the SPICE deck generating section generates a SPICE deck by interconnecting the blocks, for a path that needs analysis, by using a result of static timing analysis and using simulation conditions for the each block. The feedback-based static timing analyzing section causes a result of the simulation performed using the generated SPICE deck to be reflected in the static timing analysis.
    Type: Grant
    Filed: January 11, 2007
    Date of Patent: August 16, 2011
    Assignee: Fujitsu Limited
    Inventor: Masashi Arayama
  • Patent number: 8000953
    Abstract: Computer implemented method, system, and computer usable program code for simulating processor operation in a data processing system. An instruction trace is generated, wherein the instruction trace includes markers specified by a user for identifying interval boundaries for at least one interval of the instruction trace. The instruction trace is divided into a plurality of intervals in consideration of the markers, and the plurality of intervals are formed into a plurality of interval clusters, wherein each interval cluster represents one phase of execution of the instruction trace. At least one interval from each of the plurality of interval clusters is selected as a trace sample to provide a plurality of trace samples, wherein each selected interval is of at least a minimum size, a simulation is performed using the plurality of trace samples, and a result of the simulation is provided to the user.
    Type: Grant
    Filed: August 21, 2007
    Date of Patent: August 16, 2011
    Assignee: International Business Machines Corporation
    Inventors: Robert H. Bell, Jr., Wen-Tzer Thomas Chen, Pattabi R. Seshadri, John-David Wellman
  • Patent number: 8000941
    Abstract: A method of modeling a surface from a plurality of geometry points representing an object generally includes binning the plurality of geometry points into an n-dimensional array of cells and associating a binary value with each cell; applying a dilation algorithm to the binned plurality of geometry points to output a dilated binary representation of the plurality of geometry points; applying an erosion algorithm to the dilated binary representation of the plurality of geometry points to output a segmented volume; and applying a surface construction algorithm to the segmented volume to form a surface model of the object.
    Type: Grant
    Filed: December 30, 2007
    Date of Patent: August 16, 2011
    Assignee: St. Jude Medical, Atrial Fibrillation Division, Inc.
    Inventor: Eric Steven Olson
  • Patent number: 8000834
    Abstract: A method using a computer for generating a spiral-like tool path for milling a region of a workpiece is disclosed. The method includes the steps of: creating a family of concentric indexed circular arcs at each of two or more separate and distinct selected points within the region; determining parameters of a first set of blends to connect together the circular arcs of adjacent families of the circular arcs having an identical index to form a plurality of isoloops; determining parameters of a second set of blends for blending between adjacent isoloops to form the spiral-like tool path, and generating instructions for controlling the milling cutter in accordance with the generated tool path.
    Type: Grant
    Filed: March 11, 2010
    Date of Patent: August 16, 2011
    Assignee: Surfware, Inc.
    Inventors: Alan Diehl, Robert B. Patterson
  • Patent number: 7996193
    Abstract: A method for reducing the order of system models exploiting sparsity is disclosed. According to one embodiment, a computer-implemented method receives a system model having a first system order. The system model contains a plurality of system nodes, a plurality of system matrices. The system nodes are reordered and a reduced order system is constructed by a matrix decomposition (e.g., Cholesky or LU decomposition) on an expansion frequency without calculating a projection matrix. The reduced order system model has a lower system order than the original system model.
    Type: Grant
    Filed: April 21, 2008
    Date of Patent: August 9, 2011
    Assignee: Cadence Design Systems, Inc.
    Inventors: Zuochang Ye, Zhenhai Zhu, Joel Phillips
  • Patent number: 7996200
    Abstract: A method for transaction-based abstraction allows a comprehensive test plan to be automatically generated for a hardware design, where the test plan comprises a set of coverage points derived based on a signal classification created using transaction-based analysis to identify the architecturally-visible state of the design, using heuristic techniques to identify finite-state machines (FSMs) in a design that processes transactions, from which transaction boundaries can be identified, and wherein signals are classified based on the abstracted design as either transient, temporary, or persistent for use in developing the test plan.
    Type: Grant
    Filed: October 4, 2005
    Date of Patent: August 9, 2011
    Assignee: Synopsys, Inc.
    Inventor: James C. Wilson
  • Patent number: 7996197
    Abstract: A method for correct and efficient detection of clearances between three-dimensional bodies in computer-based simulations, where one or both of the volumes is subject to translation and/or rotations. The method conservatively determines of the size of such clearances and whether there is a collision between the bodies. Given two bodies, each of which is undergoing separate motions, the method utilizes bounding-volume hierarchy representations for the two bodies and, mappings and inverse mappings for the motions of the two bodies. The method uses the representations, mappings and direction vectors to determine the directionally furthest locations of points on the convex hulls of the volumes virtually swept by the bodies and hence the clearance between the bodies, without having to calculate the convex hulls of the bodies. The method includes clearance detection for bodies comprising convex geometrical primitives and more specific techniques for bodies comprising convex polyhedra.
    Type: Grant
    Filed: January 18, 2007
    Date of Patent: August 9, 2011
    Assignee: Sandia Corporation
    Inventor: Patrick G. Xavier
  • Patent number: 7996190
    Abstract: A solution for enhancing the identification and selection of cabling for a system, such as a computer system, is provided, which includes provisions for a virtual cabling router. As aspect of the invention provides a method of identifying cabling for a system, wherein the method comprises: identifying a placement of the plurality of components in at least one enclosure, using a virtual representation; creating a routing layout for the virtual representation, based on the placement; and identifying the cabling based on the routing layout.
    Type: Grant
    Filed: October 19, 2006
    Date of Patent: August 9, 2011
    Assignee: International Business Machines Corporation
    Inventors: Francisco R. Huizar Rodriguez, Gabriel A. Vallarta Santos
  • Patent number: 7996196
    Abstract: A first generation portion divides an object to be analyzed into a plurality of finite elements to generate element division data. A first calculation portion defines and calculates a plurality of meshes dividing the object to be analyzed into units larger than the finite elements. A second generation portion assumes that a friction layer which has a thickness of “0” and a friction coefficient between a conductive material and a composite material of a predetermined value less than 1 exists at the interface between the conductive material and the composite material, and the second generation portion generates mesh data. A second calculation portion uses various solvers to calculate the physical amounts produced in the object to be analyzed on the basis of the mesh data and outputs the analysis result. In other words, the second calculation portion performs a simulation of the behavior of the object to be analyzed.
    Type: Grant
    Filed: September 3, 2009
    Date of Patent: August 9, 2011
    Assignee: Fujitsu Limited
    Inventors: Daisuke Mizutani, Nobutaka Itoh