Abstract: An organic light-emitting diode display is disclosed. In one aspect, the display includes a substrate and a plurality of pixels formed over the substrate, each pixel including a first region from which light is emitted and a second region through which external light is transmitted. The display also includes a plurality of pixel circuit units each formed in the first region and including at least one thin-film transistor, an inorganic insulating film formed in the second region, a transparent conductive film formed over at least a portion of the inorganic insulating film, and an organic insulating film covering the pixel circuit units and at least a portion of the transparent conductive film. The display further includes a plurality of first electrodes formed over the organic insulating film and in the first regions of the pixels.

Abstract: A 3D memory has multiple memory layers stacked on top of a substrate. Word lines in different memory layers are connected respectively to different columns of contact pads in the substrate directly under the multiple memory layers. The connection is accomplished by creating vertical shifts above each contact pad and creating a vertical word line VIA connecting to the contact pad. For a given memory layer and its column of vertical word line VIAs, an auxiliary vertical shaft down to the memory layer is formed between each vertical word line VIA and an adjacent word line. The auxiliary vertical shaft is contiguous with the vertical shift allowing access to the vertical word line VIA. The auxiliary vertical shaft also enables excavating a lateral space between the word line and the vertical word line VIA. Filling the space with a conductive material completes a conductive path from the word line to the contact pad.

Abstract: One aspect of the disclosure provides for a method of forming a replacement gate structure. The method may include: removing a dummy gate from over a set of fins to form an opening in a dielectric layer exposing the set of fins, each fin in the set of fins being substantially separated from an adjacent fin in the set of fins via an dielectric; forming a protective cap layer within the opening over the exposed set of fins; removing a portion of the dielectric on each side of each fin in the set of fins; undercutting each fin by removing a portion of each fin in the set of fins to create a notch disposed under the protective cap layer; substantially filling each notch with an oxide; forming a gate dielectric over each fin in the set of fins; and forming a gate conductor over the gate dielectric, thereby forming the replacement gate structure.

Abstract: A memory structure includes a memory cell, and the memory cell includes following elements. A first gate is disposed on a substrate. A stacked structure includes a first dielectric structure, a channel layer, a second dielectric structure and a second gate disposed on the first gate, a first charge storage structure disposed in the first dielectric structure and a second charge storage structure disposed in the second dielectric structure. The first charge storage structure is a singular charge storage unit and the second charge storage structure comprises two charge storage units which are physically separated. A channel output line physically connected to the channel layer. A first dielectric layer is disposed on the first gate at two sides of the stacked structure. A first source or drain and a second source or drain are disposed on the first dielectric layer and located at two sides of the channel layer.

Abstract: A vertical-type organic light-emitting transistor for reducing the off-state leakage current to improve the current and on-off ratio includes a gate electrode, a lower semiconductor layer disposed on the gate electrode, a source electrode disposed on the lower semiconductor layer, and a source insulation film disposed on the source electrode and covering top and sides of the source electrode, wherein the lower semiconductor layer is configured such that an electric charge is injected into the lower semiconductor layer from the source electrode when voltage is applied to the gate electrode.

Abstract: Semiconductor devices and methods are provided. The semiconductor device can include a semiconductor substrate, a plurality of solder pads disposed on the semiconductor substrate, a first insulating layer disposed over the semiconductor substrate, a columnar electrode disposed over the solder pad, and a solder ball disposed on the columnar electrode. The first insulating layer can include a first opening to expose a solder pad of the plurality of solder pads. The columnar electrode can include a bulk material and a through hole in the bulk material. The through hole can expose at least a surface portion of the solder pad. The solder ball can include a convex metal head on a top surface of the bulk material of the columnar electrode, and a filling part filled in the through hole.

Abstract: A substrate having a first area and a second area is provided. The substrate is patterned to form trenches in the substrate and semiconductor fins between the trenches, wherein the semiconductor fins comprises first semiconductor fins distributed in the first area and second semiconductor fins distributed in the second area. A first fin cut process is performed in the first area to remove portions of the first semiconductor fins. Insulators are formed in the trenches after the first fin cut process is performed. A second fin cut process is performed in the second area to remove portions of the second semiconductor fins until concaves are formed between the insulators in the second area. A gate stack is formed to partially cover the first semiconductor fins, the second semiconductor fins and the insulators.

Abstract: A method for fabricating a fin field effect transistor (FinFET) comprising the following steps is provided. A substrate comprising a plurality of trenches and a plurality of semiconductor fins between the trenches is provided. A plurality of insulators are formed in the trenches. A fin cut process is performed to remove portions of the semiconductor fins until a plurality of concaves are formed between the insulators. A gate stack is formed to partially cover the semiconductor fins and the insulators.

Abstract: A method of manufacturing a semiconductor substrate includes a device-forming process of forming a plurality of device areas in a substrate section, a first wiring process of forming circuit wirings connected to the plurality of device areas, an electrode pad-forming process of forming a plurality of electrode pads, a second wiring process of forming a potential adjustment wiring electrically connecting at least a part of the electrode pads, an electrode-forming process of forming electrode bodies on the electrode pads by electroless plating after the second wiring process, and a potential adjustment-releasing process of releasing a connection by the potential adjustment wiring after the electrode-forming process.

Abstract: A semiconductor structure includes a substrate and an intrinsic replacement channel. A tunneling field effect transistor (TFET) fin may be formed by the intrinsic replacement channel, a p-fin and an n-fin formed upon the substrate. The p-fin may serve as the source of the TFET and the n-fin may serve as the drain of the TFET. The replacement channel may be formed in place of a sacrificial channel of a diode fin that includes the p-fin, the n-fin, and the sacrificial channel at the p-fin and n-fin junction.

Abstract: Various embodiments provide semiconductor packaging structures and methods for forming the same. In an exemplary method, a chip having a metal interconnect structure thereon can be provided. An insulating layer can be formed on the chip to expose the metal interconnect structure. A columnar electrode can be formed on the metal interconnect structure. A portion of the metal interconnect structure surrounding a bottom of the columnar electrode can be exposed. A diffusion barrier layer can be formed on sidewalls and a top surface of the columnar electrode, and on the exposed portion of the metal interconnect structure surrounding the bottom of the columnar electrode. A solder ball can then be formed on the diffusion barrier layer. The solder ball can wrap at least the sidewalls and the top surface of the columnar electrode.

Abstract: An organic light emitting display device includes a substrate, a first transistor disposed on the substrate in the opaque region, a second transistor disposed on the substrate in the opaque region, the second transistor being adjacent to the first transistor along a first direction, and a capacitor disposed on the substrate in the opaque region, the capacitor being adjacent to the first transistor along a second direction different from the first direction. Here, the capacitor may include a first capacitor electrode, a dielectric structure including silicon oxynitride and a second capacitor electrode.

Abstract: Embodiments of mechanisms for forming a semiconductor device are provided. The semiconductor device includes a contact pad over a substrate. The semiconductor device also includes a passivation layer over the substrate and a first portion of the contact pad, and a second portion of the contact pad is exposed through an opening. The semiconductor device further includes a post-passivation interconnect layer over the passivation layer and coupled to the second portion of the contact pad. In addition, the semiconductor device includes a bump over the post-passivation interconnect layer and outside of the opening. The semiconductor device also includes a diffusion barrier layer physically insulating the bump from the post-passivation interconnect layer while electrically connecting the bump to the post-passivation interconnect layer.

Abstract: Some embodiments include a semiconductor construction having a gate extending into a semiconductor base. Conductively-doped source and drain regions are within the base adjacent the gate. A gate dielectric has a first segment between the source region and the gate, a second segment between the drain region and the gate, and a third segment between the first and second segments. At least a portion of the gate dielectric comprises ferroelectric material. In some embodiments the ferroelectric material is within each of the first, second and third segments. In some embodiments, the ferroelectric material is within the first segment or the third segment. In some embodiments, a transistor has a gate, a source region and a drain region; and has a channel region between the source and drain regions. The transistor has a gate dielectric which contains ferroelectric material between the source region and the gate.

Abstract: An IC packaging method is provided. The method includes providing a semiconductor substrate. The semiconductor substrate has a metal pad and an insulating layer and the insulating layer has an opening to expose the meal pad. The method also includes forming an under-the-ball meal electrode on the exposed metal pad. The under-the-ball metal electrode has an electrode body and an electrode tail, the electrode body is located at a bottom portion of the under-the-ball metal electrode and is in contact with the metal pad, and the electrode tail is located at a top portion of the under-the-ball meal electrode. Further, the method includes forming a solder ball on the under-the-ball metal electrode.

Abstract: An integrated circuit is provided. The integrated circuit includes a substrate, a first FinFET device supported by the substrate, the first FinFET device having a first fin with a non-tiered fin profile, and a second FinFET supported by the substrate, the second FinFET having a second fin with a tiered fin profile.

Abstract: A semiconductor device includes a gate, a first electrode, a first insulating layer, an active layer, an etching stop layer, a second insulating layer, a source, a drain and a second electrode. The first insulating layer covers the gate and the first electrode. The active layer and the etching stop layer are disposed on the first insulating layer above the gate and the first electrode respectively. The second insulating layer covers the active layer and the etching stop layer and has a first opening and a second opening exposing the active layer and a third opening exposing the etching stop layer. The source and the drain are disposed on the second insulating layer and contact with the active layer through the first opening and the second opening respectively. The second electrode is located on the second insulating layer and contacts with the etching stop layer through the third opening.

Abstract: A method for fabricating a semiconductor device includes forming a first hard mask (HM) layer over a material layer, forming a patterned second HM layer over the first HM layer. The patterned second HM layer has first trench extending along a first direction. The method also includes forming a patterned resist layer over the second HM layer. The patterned resist layer has a first line opening extending along a second direction, which is perpendicular to the first direction. The first line opening overlaps the first trench and exposes a portion of the second HM layer. The method also includes etching the first HM layer by using the patterned resist layer and the exposed portion of the second HM layer as an etch mask together to form a first hole feature in the first HM layer.

Abstract: A semiconductor device of an embodiment includes: an insulating film including: a first region extending in a first direction; second and third regions arranged at a distance from each other; and fourth and fifth regions each having a concave shape, the fourth and fifth regions each having a smaller film thickness than a film thickness of each of the first through third regions; a semiconductor layer formed in a direction from the fourth region toward the fifth region, the semiconductor layer having a smaller width than a width of each of source and drain regions, the semiconductor layer being connected to the source and drain regions; a gate electrode placed on the opposite side of a gate insulating film from the semiconductor layer on the first region; and a gate sidewall formed on a side face of the gate electrode.

Abstract: There is disclosed a method for manufacturing an Electro Static Discharge (ESD) device, an ESD device and a display panel, which are capable of addressing an issue that static-electric charges accumulated on the array substrate damage the unformed ESD device and improving a yield ratio of the array substrate. The method includes forming a TFT, a first lead wire, wherein the first lead wire or the second lead wire comprises at least two separate lead-wire segments; depositing a layer of passivation thin film, and forming via-holes for connecting the at least two separate lead-wire segments on the layer of passivation thin film; depositing a layer of transparent conductive film on the substrate on which the via-holes are formed, wherein the layer of transparent conductive film connects the lead-wire segments by the via-holes.