Patents Examined by Pavel G. Ivanov
  • Patent number: 11114535
    Abstract: A semiconductor device may include a substrate including a fin active region extending in a first direction, a gate structure crossing the fin active region and extending in a second direction crossing the first direction, source/drain regions on the fin active region at opposite sides of the gate structure, a first contact structure electrically connected to one of the source/drain regions, a pair of first contact block structures on opposite first sidewalls, respectively, of the first contact structure in the second direction.
    Type: Grant
    Filed: October 5, 2018
    Date of Patent: September 7, 2021
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Hak-yoon Ahn, Sang-hyun Lee, Sung-woo Kang, Hong-sik Shin, Seong-han Oh, Young-mook Oh, In-keun Lee
  • Patent number: 11075270
    Abstract: The present disclosure provides a semiconductor structure and a method for forming the same. The method includes: providing a base, the base including a source-drain doped region and an interlayer dielectric layer over the source-drain doped region; etching the interlayer dielectric layer to form an opening that exposes the source-drain doped region; and forming a first doped region at the top of the source-drain doped region exposed by the opening and a second doped region over the first doped region, a projection of the second doped region on the base covering a projection of the first doped region on the base, the doping ion types of the first doped region, the second doped region and the source-drain doped region being the same, and the ion doping concentration of the first doped region and the second doped region being higher than the ion doping concentration of the source-drain doped region.
    Type: Grant
    Filed: October 15, 2019
    Date of Patent: July 27, 2021
    Assignees: Semiconductor Manufacturing (Shanghai) International Corporation, Semiconductor Manufacturing (Beijing) International Corporation
    Inventor: Zhaomeng
  • Patent number: 11063119
    Abstract: Disclosed are a semiconductor structure and a method for forming same.
    Type: Grant
    Filed: October 15, 2019
    Date of Patent: July 13, 2021
    Assignees: Semiconductor Manufacturing (Beijing) International Corporation, Semiconductor Manufacturing (Shanghai) International Corporation
    Inventor: Nan Wang
  • Patent number: 11031244
    Abstract: A method for improving EUV lithographic patterning of SnO2 layers is provided. One method embodiment includes introducing a hydrophobic surface treatment compound into a processing chamber for modifying a surface of an SnO2 layer. The modification increases the hydrophobicity of the SnO2 layer. The method also provides for depositing a photoresist layer on the surface of the SnO2 layer via spin coating. The modification of the surface of the SnO2 layer enhances adhesion of contact between the photoresist and the SnO2 layer during and after spin coating.
    Type: Grant
    Filed: August 14, 2018
    Date of Patent: June 8, 2021
    Assignee: Lam Research Corporation
    Inventors: Akhil Singhal, Nader Shamma, Dustin Zachary Austin
  • Patent number: 11011433
    Abstract: A method includes forming a gate stack of a transistor. The formation of the gate stack includes forming a silicon oxide layer on a semiconductor region, depositing a hafnium oxide layer over the silicon oxide layer, depositing a lanthanum oxide layer over the hafnium oxide layer, and depositing a work-function layer over the lanthanum oxide layer. Source/drain regions are formed on opposite sides of the gate stack.
    Type: Grant
    Filed: April 20, 2020
    Date of Patent: May 18, 2021
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Shahaji B. More, Zheng-Yang Pan, Shih-Chieh Chang, Chun-Chieh Wang
  • Patent number: 11004765
    Abstract: A semiconductor device may include a semiconductor substrate, an insulator film covering a part of an upper surface of the substrate, and a gate electrode opposing the upper surface via the insulator film. In the semiconductor substrate, a drift layer extending through a body layer to the upper surface opposes the gate electrode via the insulator film. The insulator film extends from the upper surface of the semiconductor substrate to an upper surface of the gate electrode by passing between the gate electrode and an upper electrode, and defines an opening at the upper surface of the gate electrode. A side surface of the opening of the insulator film is entirely located outside a volume space consisting of all straight lines that passes through the opposing surface of the drift layer at angle of 45 degrees to the opposing surface.
    Type: Grant
    Filed: October 29, 2019
    Date of Patent: May 11, 2021
    Assignee: DENSO CORPORATION
    Inventors: Jun Saito, Yusuke Yamashita, Yasushi Urakami
  • Patent number: 11004684
    Abstract: A catalyst is imparted selectively to a plateable material portion 32 by performing a catalyst imparting processing on a substrate W having a non-plateable material portion 31 and the plateable material portion 32 formed on a surface thereof. Then, a hard mask layer 35 is formed selectively on the plateable material portion 32 by performing a plating processing on the substrate W. The non-plateable material portion 31 is made of SiO2 as a main component, and the plateable material portion 32 is made of a material including, as a main component, a material containing at least one of a OCHx group and a NHx group, a metal material containing Si as a main component, a material containing carbon as a main component or a catalyst metal material.
    Type: Grant
    Filed: January 22, 2019
    Date of Patent: May 11, 2021
    Assignee: TOKYO ELECTRON LIMITED
    Inventors: Mitsuaki Iwashita, Takeshi Nagao, Nobutaka Mizutani, Takashi Tanaka, Koichi Yatsuda, Kazutoshi Iwai, Yuichiro Inatomi
  • Patent number: 10971622
    Abstract: A transistor structure includes a substrate and a fin structure on the substrate. The fin structure includes an undoped portion, a first doped portion, and a second doped portion. The transistor structure includes an electrode on the fin structure between the first doped portion and the second doped portion, and an insulating layer on the fin structure. The transistor structure includes a first trench in the insulating layer at a first side of the fin structure and between the electrode and the second doped portion, and a second trench in the insulating layer at a second side of the fin structure and between the electrode and the second doped portion. The first trench includes a first conductive material, and the second trench includes a second conductive material.
    Type: Grant
    Filed: October 5, 2018
    Date of Patent: April 6, 2021
    Assignee: Avago Technologies International Sales Pte. Limited
    Inventors: Qing Liu, Akira Ito
  • Patent number: 10950426
    Abstract: A method for manufacturing a dielectric layer includes forming a first dielectric film over a substrate. A first porogen is deposited over the first dielectric film. A second dielectric film is formed on and in contact with the first dielectric film and the first porogen. The first porogen is removed.
    Type: Grant
    Filed: August 14, 2018
    Date of Patent: March 16, 2021
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Yi-Chen Ho, You-Hua Chou, Yen-Hao Liao, Che-Lun Chang, Zhen-Cheng Wu
  • Patent number: 10903283
    Abstract: A display device includes a substrate with a display region and a non-display region. First to third pixels are in the display region and have emission regions to emit light from corresponding light emitting elements. Pixel circuit areas in the first to third pixels drive the light emitting elements. A dummy pattern is in a non-emission region, except the emission region. The dummy pattern extends along the extending direction of one pixel among the first to third pixels. A thin film encapsulation layer covers the dummy pattern and the light emitting element.
    Type: Grant
    Filed: July 5, 2018
    Date of Patent: January 26, 2021
    Assignee: SAMSUNG DISPLAY CO., LTD.
    Inventor: Jin Baek Choi
  • Patent number: 10892354
    Abstract: Dual-base two-sided bipolar power transistors which use an insulated field plate to separate the emitter/collector diffusions from the nearest base contact diffusion. This provides a surprising improvement in turn-off performance, and in breakdown voltage.
    Type: Grant
    Filed: January 27, 2020
    Date of Patent: January 12, 2021
    Assignee: Ideal Power Inc.
    Inventors: William C. Alexander, Richard A. Blanchard
  • Patent number: 10886220
    Abstract: For a semiconductor integrated circuit device in which IO cells are disposed, power supply voltage drop can be reduced using a multilayer interconnect. A power supply interconnect formed in a plurality of interconnect layers extends in an X direction that is a same direction as a direction in which the IO cells are aligned. In an area of a power supply IO cell, a power supply interconnect extending in a Y direction is disposed in one of the interconnect layers in which the power supply interconnect is not formed and an interconnect piece is disposed in a same position as a position of the power supply interconnect formed in an area of a signal IO cell in the Y direction at each of both ends of the area of the power supply IO cell in the X direction.
    Type: Grant
    Filed: August 29, 2019
    Date of Patent: January 5, 2021
    Assignee: SOCIONEXT INC.
    Inventors: Chika Ito, Isaya Sobue
  • Patent number: 10865501
    Abstract: A silicon carbide epitaxial substrate has a silicon carbide single-crystal substrate and a silicon carbide layer. A first ratio of an absolute value of a difference between a dopant density in a first end region and a dopant density in a central region to an average value of the dopant density in the first end region and the dopant density in the central region is not more than 40%. A second ratio of an absolute value of a difference between a dopant density in a second end region and the dopant density in the central region to an average value of the dopant density in the second end region and the dopant density in the central region is not more than 40%.
    Type: Grant
    Filed: July 4, 2016
    Date of Patent: December 15, 2020
    Assignee: Sumitomo Electric Industries, Ltd.
    Inventors: Tsutomu Hori, Hironori Itoh
  • Patent number: 10818854
    Abstract: In a flexible organic light-emitting display device according to the present disclosure, an organic sealing film having a refractive index at least 0.3 smaller than a refractive index of each of first and second inorganic sealing films is disposed between the first and second inorganic sealing films, and, at the same time, a thickness of a front sealing layer is optimized to be less than 10 micrometers inclusive. Thus, the refractive index difference between the organic capping layer and the inorganic capping layer may be maximized to increase the micro-cavity effect. Further, by increasing the refractive index difference and optimizing the thickness in the front sealing layer, the micro-cavity effect may further be increased and, hence, the light extraction efficiency may be maximized.
    Type: Grant
    Filed: August 10, 2018
    Date of Patent: October 27, 2020
    Assignee: LG Display Co., Ltd.
    Inventors: Jinho Park, Sanggun Lee, Donghyeok Lim
  • Patent number: 10811433
    Abstract: One illustrative device disclosed herein is formed on an SOI substrate. The transistor device includes a first channel region formed in a semiconductor bulk substrate of the SOI substrate and a first gate insulation layer formed above the first channel region. In one embodiment, the first gate insulation layer includes a part of the buried insulation layer of the SOI substrate and an oxidized part of the semiconductor layer of the SOI substrate.
    Type: Grant
    Filed: June 20, 2019
    Date of Patent: October 20, 2020
    Assignee: GLOBALFOUNDRIES Inc.
    Inventors: Elliot John Smith, Nigel Chan, Nilesh Kenkare
  • Patent number: 10770290
    Abstract: A semiconductor device includes a substrate, a first semiconductor stack including elongated semiconductor features isolated from each other and overlaid in a direction perpendicular to a top surface of the substrate, and a second semiconductor stack including elongated semiconductor features isolated from each other and overlaid in the direction perpendicular to the top surface of the substrate. The second semiconductor stack has different geometric characteristics than the first semiconductor stack. A top surface of the first semiconductor stack is coplanar with a top surface of the second semiconductor stack.
    Type: Grant
    Filed: July 12, 2018
    Date of Patent: September 8, 2020
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD
    Inventors: Tung Ying Lee, Shao-Ming Yu
  • Patent number: 10720597
    Abstract: An electroluminescent display device includes: a substrate including a subpixel; a thin film transistor disposed at the subpixel; an overcoat layer disposed on the thin film transistor; a first electrode disposed on the overcoat layer and electrically connected to the thin film transistor; a bank layer disposed on the overcoat layer and the first electrode, the bank layer including a plurality of openings configured to expose the first electrode and a plurality of opening patterns formed in a bar shape to expose the first electrode and connect the plurality of openings; an emitting layer disposed on the first electrode and the bank layer; and a second electrode disposed on the emitting layer.
    Type: Grant
    Filed: August 22, 2018
    Date of Patent: July 21, 2020
    Assignee: LG Display Co., Ltd.
    Inventors: Yong-Hoon Choi, Keum-Kyu Min, Won-Hoe Koo
  • Patent number: 10629496
    Abstract: A method includes forming a gate stack of a transistor. The formation of the gate stack includes forming a silicon oxide layer on a semiconductor region, depositing a hafnium oxide layer over the silicon oxide layer, depositing a lanthanum oxide layer over the hafnium oxide layer, and depositing a work-function layer over the lanthanum oxide layer. Source/drain regions are formed on opposite sides of the gate stack.
    Type: Grant
    Filed: July 31, 2017
    Date of Patent: April 21, 2020
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Shahaji B. More, Zheng-Yang Pan, Chun-Chieh Wang, Shih-Chieh Chang
  • Patent number: 10580885
    Abstract: Dual-base two-sided bipolar power transistors which use an insulated field plate to separate the emitter/collector diffusions from the nearest base contact diffusion. This provides a surprising improvement in turn-off performance, and in breakdown voltage.
    Type: Grant
    Filed: August 30, 2019
    Date of Patent: March 3, 2020
    Assignee: Ideal Power, Inc.
    Inventors: William C. Alexander, Richard A. Blanchard
  • Patent number: 10553538
    Abstract: Semiconductor packages having variable redistribution layer thicknesses are described. In an example, a semiconductor package includes a redistribution layer on a dielectric layer, and the redistribution layer includes first conductive traces having a first thickness and second conductive traces having a second thickness. The first thickness may be different than the second thickness, e.g., the first thickness may be less than the second thickness.
    Type: Grant
    Filed: October 4, 2018
    Date of Patent: February 4, 2020
    Assignee: Intel Corporation
    Inventors: Klaus J├╝rgen Reingruber, Sven Albers, Christian Georg Geissler, Georg Seidemann, Bernd Waidhas, Thomas Wagner, Marc Dittes