Abstract: A memory device includes a substrate; a bottom electrode disposed over the substrate; an insulating layer disposed over the bottom electrode, the insulating layer having a through hole defined in the insulating layer; a heater disposed in the through hole; a phase change material layer disposed over the heater; a selector layer disposed over the phase change material layer; and a metal layer disposed over the selector layer. The metal layer is wider than the phase change material layer.

Abstract: A semiconductor device may include a substrate including a fin active region extending in a first direction, a gate structure crossing the fin active region and extending in a second direction crossing the first direction, source/drain regions on the fin active region at opposite sides of the gate structure, a first contact structure electrically connected to one of the source/drain regions, a pair of first contact block structures on opposite first sidewalls, respectively, of the first contact structure in the second direction.

Abstract: The present disclosure provides a semiconductor structure and a method for forming the same. The method includes: providing a base, the base including a source-drain doped region and an interlayer dielectric layer over the source-drain doped region; etching the interlayer dielectric layer to form an opening that exposes the source-drain doped region; and forming a first doped region at the top of the source-drain doped region exposed by the opening and a second doped region over the first doped region, a projection of the second doped region on the base covering a projection of the first doped region on the base, the doping ion types of the first doped region, the second doped region and the source-drain doped region being the same, and the ion doping concentration of the first doped region and the second doped region being higher than the ion doping concentration of the source-drain doped region.

Abstract: Disclosed are a semiconductor structure and a method for forming same.

Abstract: A method for improving EUV lithographic patterning of SnO2 layers is provided. One method embodiment includes introducing a hydrophobic surface treatment compound into a processing chamber for modifying a surface of an SnO2 layer. The modification increases the hydrophobicity of the SnO2 layer. The method also provides for depositing a photoresist layer on the surface of the SnO2 layer via spin coating. The modification of the surface of the SnO2 layer enhances adhesion of contact between the photoresist and the SnO2 layer during and after spin coating.

Abstract: A method includes forming a gate stack of a transistor. The formation of the gate stack includes forming a silicon oxide layer on a semiconductor region, depositing a hafnium oxide layer over the silicon oxide layer, depositing a lanthanum oxide layer over the hafnium oxide layer, and depositing a work-function layer over the lanthanum oxide layer. Source/drain regions are formed on opposite sides of the gate stack.

Abstract: A catalyst is imparted selectively to a plateable material portion 32 by performing a catalyst imparting processing on a substrate W having a non-plateable material portion 31 and the plateable material portion 32 formed on a surface thereof. Then, a hard mask layer 35 is formed selectively on the plateable material portion 32 by performing a plating processing on the substrate W. The non-plateable material portion 31 is made of SiO2 as a main component, and the plateable material portion 32 is made of a material including, as a main component, a material containing at least one of a OCHx group and a NHx group, a metal material containing Si as a main component, a material containing carbon as a main component or a catalyst metal material.

Abstract: A semiconductor device may include a semiconductor substrate, an insulator film covering a part of an upper surface of the substrate, and a gate electrode opposing the upper surface via the insulator film. In the semiconductor substrate, a drift layer extending through a body layer to the upper surface opposes the gate electrode via the insulator film. The insulator film extends from the upper surface of the semiconductor substrate to an upper surface of the gate electrode by passing between the gate electrode and an upper electrode, and defines an opening at the upper surface of the gate electrode. A side surface of the opening of the insulator film is entirely located outside a volume space consisting of all straight lines that passes through the opposing surface of the drift layer at angle of 45 degrees to the opposing surface.

Abstract: A transistor structure includes a substrate and a fin structure on the substrate. The fin structure includes an undoped portion, a first doped portion, and a second doped portion. The transistor structure includes an electrode on the fin structure between the first doped portion and the second doped portion, and an insulating layer on the fin structure. The transistor structure includes a first trench in the insulating layer at a first side of the fin structure and between the electrode and the second doped portion, and a second trench in the insulating layer at a second side of the fin structure and between the electrode and the second doped portion. The first trench includes a first conductive material, and the second trench includes a second conductive material.

Abstract: A method for manufacturing a dielectric layer includes forming a first dielectric film over a substrate. A first porogen is deposited over the first dielectric film. A second dielectric film is formed on and in contact with the first dielectric film and the first porogen. The first porogen is removed.

Abstract: A display device includes a substrate with a display region and a non-display region. First to third pixels are in the display region and have emission regions to emit light from corresponding light emitting elements. Pixel circuit areas in the first to third pixels drive the light emitting elements. A dummy pattern is in a non-emission region, except the emission region. The dummy pattern extends along the extending direction of one pixel among the first to third pixels. A thin film encapsulation layer covers the dummy pattern and the light emitting element.

Abstract: Dual-base two-sided bipolar power transistors which use an insulated field plate to separate the emitter/collector diffusions from the nearest base contact diffusion. This provides a surprising improvement in turn-off performance, and in breakdown voltage.

Abstract: For a semiconductor integrated circuit device in which IO cells are disposed, power supply voltage drop can be reduced using a multilayer interconnect. A power supply interconnect formed in a plurality of interconnect layers extends in an X direction that is a same direction as a direction in which the IO cells are aligned. In an area of a power supply IO cell, a power supply interconnect extending in a Y direction is disposed in one of the interconnect layers in which the power supply interconnect is not formed and an interconnect piece is disposed in a same position as a position of the power supply interconnect formed in an area of a signal IO cell in the Y direction at each of both ends of the area of the power supply IO cell in the X direction.

Abstract: A silicon carbide epitaxial substrate has a silicon carbide single-crystal substrate and a silicon carbide layer. A first ratio of an absolute value of a difference between a dopant density in a first end region and a dopant density in a central region to an average value of the dopant density in the first end region and the dopant density in the central region is not more than 40%. A second ratio of an absolute value of a difference between a dopant density in a second end region and the dopant density in the central region to an average value of the dopant density in the second end region and the dopant density in the central region is not more than 40%.

Abstract: In a flexible organic light-emitting display device according to the present disclosure, an organic sealing film having a refractive index at least 0.3 smaller than a refractive index of each of first and second inorganic sealing films is disposed between the first and second inorganic sealing films, and, at the same time, a thickness of a front sealing layer is optimized to be less than 10 micrometers inclusive. Thus, the refractive index difference between the organic capping layer and the inorganic capping layer may be maximized to increase the micro-cavity effect. Further, by increasing the refractive index difference and optimizing the thickness in the front sealing layer, the micro-cavity effect may further be increased and, hence, the light extraction efficiency may be maximized.

Abstract: One illustrative device disclosed herein is formed on an SOI substrate. The transistor device includes a first channel region formed in a semiconductor bulk substrate of the SOI substrate and a first gate insulation layer formed above the first channel region. In one embodiment, the first gate insulation layer includes a part of the buried insulation layer of the SOI substrate and an oxidized part of the semiconductor layer of the SOI substrate.

Abstract: A semiconductor device includes a substrate, a first semiconductor stack including elongated semiconductor features isolated from each other and overlaid in a direction perpendicular to a top surface of the substrate, and a second semiconductor stack including elongated semiconductor features isolated from each other and overlaid in the direction perpendicular to the top surface of the substrate. The second semiconductor stack has different geometric characteristics than the first semiconductor stack. A top surface of the first semiconductor stack is coplanar with a top surface of the second semiconductor stack.

Abstract: An electroluminescent display device includes: a substrate including a subpixel; a thin film transistor disposed at the subpixel; an overcoat layer disposed on the thin film transistor; a first electrode disposed on the overcoat layer and electrically connected to the thin film transistor; a bank layer disposed on the overcoat layer and the first electrode, the bank layer including a plurality of openings configured to expose the first electrode and a plurality of opening patterns formed in a bar shape to expose the first electrode and connect the plurality of openings; an emitting layer disposed on the first electrode and the bank layer; and a second electrode disposed on the emitting layer.

Abstract: A method includes forming a gate stack of a transistor. The formation of the gate stack includes forming a silicon oxide layer on a semiconductor region, depositing a hafnium oxide layer over the silicon oxide layer, depositing a lanthanum oxide layer over the hafnium oxide layer, and depositing a work-function layer over the lanthanum oxide layer. Source/drain regions are formed on opposite sides of the gate stack.

Abstract: Dual-base two-sided bipolar power transistors which use an insulated field plate to separate the emitter/collector diffusions from the nearest base contact diffusion. This provides a surprising improvement in turn-off performance, and in breakdown voltage.