Patents Examined by Peter J. Corcoran, III
  • Patent number: 6064819
    Abstract: Selected code is modeled in a polyhedral dependency graph (PDG). A placement optimizer maps each element of the PDG to an optimally placed PDG. An ordering optimizer maps the placed PDG to an optimally ordered PDG. The PDG, place PDG, and ordered PDG are combined to produce a transformation script. The transformation script is applied to the selected specification description to produce optimized selected code. Optimized selected code is combined with original code to generate a control-flow optimized code. In addition, memory directives are derived from the ordered PDG model. The memory directives and optimized code are used to generate target code for simulation or software compilation.
    Type: Grant
    Filed: April 2, 1997
    Date of Patent: May 16, 2000
    Assignee: Imec
    Inventors: Frank Franssen, Michael van Swaaij, Lode Nachtergaele, Hans Samsom, Francky Catthoor, Hugo De Man
  • Patent number: 5991538
    Abstract: An object-oriented development system of the present invention includes a development system, which may include, among other features, a compiler, a linker, standard libraries, class libraries, and a debugger. Methods of the present invention include constructing C++ classes having response functions--C++ class methods which process specific system messages of interest. More particularly, a C++ class includes a registry object--an object which associates the message of interest with a particular response function. The registry object includes C++ template definition, whereby the object includes a "generic" function, that is, one which is not tied to any specific parameter type. In this manner, the message-response functions of the development system do not require compiler-specific extensions or unsafe casting operations.
    Type: Grant
    Filed: December 18, 1992
    Date of Patent: November 23, 1999
    Assignee: Inprise Corporation
    Inventor: Peter J. Becker
  • Patent number: 5970244
    Abstract: A control flow is prepared by connecting blocks in an execution order, each block not including a branch and comprising a series of statement, based on a syntactical analysis of a program. A second control flow is prepared by cutting the first control flow at one portion and combining the cut result with a symbol designating a loop. A third control flow is prepared by expressing a portion of a loop, branch and merge in the second control flow and the second control flow in a hierarchical manner. The third control flow expresses a portion of a sequential execution other than the loop, branch and merge, a portion of the loop, and a portion of a branch and merge in a hierarchical order by using a symbol for a sequential execution. A specification of the program is extracted by using the third control flow.
    Type: Grant
    Filed: June 30, 1995
    Date of Patent: October 19, 1999
    Assignee: Fujitsu Limited
    Inventors: Kenji Nagahashi, Sanya Uehara
  • Patent number: 5956512
    Abstract: A debugger is used in an environment of optimized compiling to track both user-defined and synthesized variables so that the values of these variables at selected programmer counter addresses can be either determined or set. The tracking is primarily accomplished by the generation of various interrelated tables including a Type Scope Table, a Name Space Table, an Expression Table, a Location Range Tab and a Variable Table. These tables define the existence of variable at defined program counter ranges and provide the algebraic definitions for the synthesized variables. A programmer can efficiently debug a program produced with optimized compiling through the operations of determining variable values and setting variable values.
    Type: Grant
    Filed: September 29, 1995
    Date of Patent: September 21, 1999
    Assignee: Hewlett-Packard Co.
    Inventors: Steven M. Simmons, Gary S. Brooks
  • Patent number: 5943498
    Abstract: A system provides debugging functions for high-speed processors by adding a comparatively small amount of hardware to the microprocessor. A debugging module which receives part of the debugging function is placed in a microprocessor and is connected with a debugging tool outside the processor. In the debugging module, a processor core in the processor accesses and executes a monitor program in the debugging tool 60 through the debugging module. In the normal mode, while the processor executes a user program, the debugging module receives trace information and sends it to the debugging tool and also performs tasks related to the breakpoints.
    Type: Grant
    Filed: December 28, 1995
    Date of Patent: August 24, 1999
    Assignee: Hewlett-Packard Company
    Inventors: Tatsuo Yano, Takashi Miyamori
  • Patent number: 5940619
    Abstract: In a computerized method, a computer program is analyzed while the program is interpreted. The program is expressed in a first memory as input values and functions. Some of the input values are complex values which can have a plurality of component values. Each function operates on combinations of the input values and the functions of the program. The program is interpreted in a processor connected to the first memory. The processor is also connected to a second memory to store result values produced during the interpretation. Selected input values, components of the complex values, and functions are named only if the selected values, components, and functions are necessary to produce a selected result value. For each function of the program, the function which is interpreted, the input values on which the function depends, and the result value produced by the function during interpretation, are recorded in the second memory to dynamically perform a precise dependency analysis of the program.
    Type: Grant
    Filed: October 25, 1996
    Date of Patent: August 17, 1999
    Assignee: Digital Equipment Corporation
    Inventors: Martin Abadi, James J. Horning, Butler W. Lampson, Roy Levin, Jean-Jacques Levy, Yuan Yu
  • Patent number: 5937194
    Abstract: A data-parallel reduction operation is performed by a group of threads, a rope, participating in a multi-level two-phase tree structure: a fan-in computation phase followed by a fan-out broadcast phase. Local reductions are performed at each subtree during the fan-in phase, and the final reduced value is broadcast to all the threads during the fan-out phase. As the reduction operation is a data-parallel operation, the reduction operation is rope specific and is provided by the use of a parallel computation skeleton which is a fan-in followed by the fan-out, a data-type specific binary operation, and a final broadcast that takes place in the reduction operation. When the rope object is constructed, the parallel computation skeleton is automatically constructed. The threads in a rope may perform type-specific reduction operations by cloning this parallel computation skeleton to a data-type specific reduction object for that type.
    Type: Grant
    Filed: March 12, 1997
    Date of Patent: August 10, 1999
    Assignee: International Business Machines Corporation
    Inventor: Neelakantan Sundaresan
  • Patent number: 5937190
    Abstract: A digital circuit is synthesized from a text description of a digital system. During synthesis, a parse tree with parse nodes is constructed and retained. The relationship between the parse nodes and the circuit elements synthesized from those parse nodes is retained. Using that relationship, analysis results associated with circuit elements can be related to the text that generated those circuit elements. In particular, the analysis results can be used to set the display characteristics, such as font or size, of the text associated with those results.
    Type: Grant
    Filed: April 3, 1995
    Date of Patent: August 10, 1999
    Assignee: Synopsys, Inc.
    Inventors: Brent Gregory, Trinanjan Chatterjee, Jing C. Lin, Srinivas Raghvendra, Emil Girczyc, Paul Estrada, Andrew Seawright
  • Patent number: 5933640
    Abstract: A computer implemented method analyzes an execution of a program. The method partitions the program into program components such as basic blocks and procedures. A source or executable representation of the program is instrumented to collect test coverage data. In addition, a flow graph representing the program components is generated. The program is then executed to collect test coverage data. Using the test coverage data and the flow graph, the program is partitioned into executed and unexecuted components. The number of instructions in each unexecuted program component is counted. Thus, a list of the unexecuted program components can be presented according to a decreasing order of the number of unexecuted instructions in the unexecuted program components.
    Type: Grant
    Filed: February 26, 1997
    Date of Patent: August 3, 1999
    Assignee: Digital Equipment Corporation
    Inventor: Jeremy Dion
  • Patent number: 5933636
    Abstract: The present invention is a method for creating common functionality software units suitable for controlling a telecommunications switch. The common functionality software units are created by performing a domain analysis on all existing telecommunication switches which results in the identification of common concepts, terminology, behavior, and functionality for all possible combinations of Bearer Service Handlers (BSHs) and types of hardware (HW) for the switches. The common behavior and functionality is implemented in a Universal Common Software Template (UCST), an associated Parameter Definition Document (PDD), and an associated Collection of Abstract Data Type Definitions (CADTD). The UCST is compiled and tested with a subset of the CADTD. After the UCST is compiled and tested, a plurality of common software function units (CSs) for the different combinations of BSH and HW may be created from the UCST and the CADTD.
    Type: Grant
    Filed: April 24, 1997
    Date of Patent: August 3, 1999
    Assignee: Telefonktiebolaget LM Ericsson
    Inventor: Fredrik Svanfeldt
  • Patent number: 5926639
    Abstract: A method and apparatus for making flow information available for binary manipulation tasks are disclosed. Flow information is generated and saved either by a compiler or by a flow information generator. A compiler generates the flow information directly from a source file while the compiler is compiling the source file into an executable file. A flow information generator generates the flow information from an executable file in a manner similar to a compiler. Further, the flow information generator groups the executable file into units of text and traces the units to produce the flow information. The binary information thus retrieved is saved and embedded either in a text or a header of the executable file or placed in a file separate from the executable file. The flow information may be used in binary manipulations including binary translations, binary-to-binary optimizations, program tracing, and program debugging.
    Type: Grant
    Filed: December 18, 1996
    Date of Patent: July 20, 1999
    Assignee: Sun Microsystems, Inc.
    Inventor: Stephen E. Richardson
  • Patent number: 5923880
    Abstract: The present invention provides an improved method and apparatus for generating executable computer code for an application program written in C++ source code. In typical prior art systems, application program source code that has not itself been modified must still generally be recompiled in the event that object-oriented class definitions used by the application program and contained in separate header files have been modified. The methods and apparatus of the present invention reduce the need for such recompilation, by using procedural interfaces to implement object-oriented interfaces at the compiled code level. Thus, in accordance with the present invention, compiled header file code is generated that includes accessors for accessing object instances of the class definitions, each of the accessors being a procedure operative to access the object instances of the corresponding class definition.
    Type: Grant
    Filed: May 1, 1998
    Date of Patent: July 13, 1999
    Assignee: Sun Microsystems, Inc.
    Inventors: John R. Rose, Wayne C. Gramlich
  • Patent number: 5920719
    Abstract: A hierarchical registration architecture manages and organizes the collection of performance information, such as statistics and tracing, for an extensible operating system of a computer. The registration architecture, or registry, comprises a multi-linked tree data structure within a main memory for accessing the performance information. Writer entities register their intent to collect and store performance information in the registry by creating objects, via novel API calls, as nodes organized within the tree structure. Each object node of the registry is named according to a convention that identifies the type of performance data collected by that node. Each object node further represents a single data item having a single data type for collecting the performance and a reference to the actual storage location of its collected performance information. Information storage preferably occurs in globally-shared memory so that any software entity can access the information.
    Type: Grant
    Filed: November 6, 1995
    Date of Patent: July 6, 1999
    Assignee: Apple Computer, Inc.
    Inventors: Carl D. Sutton, Marianne Hsien-Ming Hsiung
  • Patent number: 5915115
    Abstract: A model information control system ("MICS") is used in conjunction with a user-defined information model and one or more conventional information system program modules or "functions" to execute business applications. The MICS includes an event-action-state machine that manipulates the user-defined information model and the functions.
    Type: Grant
    Filed: November 14, 1996
    Date of Patent: June 22, 1999
    Inventor: Kirit K. Talati
  • Patent number: 5905891
    Abstract: A programmable controller (PC) which converts PC instructions directly into targeted CPU instructions, not into a macroprogram format, and stores them as an execution file. The PC stores restoration information for ladder display together with the CPU instructions, whereby the number of program steps to be executed is reduced and a ladder display can be provided. The PC also converts PC instructions written in the ladder language into restoration information restorable to the ladder language and generates them as a main processing restoration information file, then converts the PC instructions directly into targeted CPU instructions, not into a macroprogram format, on the basis of the restoration information file, and stores them as an execution file independently of the main processing restoration information file.
    Type: Grant
    Filed: January 23, 1995
    Date of Patent: May 18, 1999
    Assignee: Mitsubishi Denki Kabushiki Kaisha
    Inventors: Toshio Harada, Kazuhiro Kudo
  • Patent number: 5905890
    Abstract: An event system is provided within an object-oriented environment. The event system informs users and system functions of events within the system. Events may be modeled as objects that are visible within the global namespace. These objects include event source objects and event sink objects. Event source objects generate event reports and event sink objects are the objects that receive reports. Special objects may be incorporated in the system to direct event reports from an event source object to an event sink object.
    Type: Grant
    Filed: May 25, 1995
    Date of Patent: May 18, 1999
    Assignee: Microsoft Corporation
    Inventors: Michael R. C. Seaman, Kevin W. Ross, Mark S. Blanford, Isaac J. Heizer, Daniel E. F. Plastina
  • Patent number: 5903762
    Abstract: A client computer obtains an execution file name of an application to be started from the constitution file information thereof and notifies the application distribution request information to a server computer and upon receipt of it, the server computer obtains the execution file name of the application, distributes a file constituting the application to the client computer when the client computer is registered in the license information, decides whether the distribution of the application succeeds or not from the notification result, and starts the application by the client computer. By doing this, generation and use of an application program are realized in the same development environment and even if an application in the client computer is updated at the start of the application, an application requested to the client computer from the server computer can be set up automatically and remotely.
    Type: Grant
    Filed: May 5, 1997
    Date of Patent: May 11, 1999
    Assignee: Hitachi, Ltd.
    Inventors: Kazuhiko Sakamoto, Masasuke Tominaga, Tetsuya Masuishi, Matsuki Yoshino
  • Patent number: 5903757
    Abstract: A computer system monitors a variety of conditions indicating levels to which different components, services and resources are being utilized, and based on these levels, determines a measure of overall system utilization. By way of example, the conditions are CPU utilizations dispatcher queue length, number of active users, number of users in an I/O wait queue and the paging rate. The system determines and repeatedly updates a data value for each of the conditions representing a respective amount of utilization. Then, the system determines a weighted summation based on the latest update of the data values and a significance of each of the data values in indicating system utilization. Next, the system compares the weighted summation to two or more thresholds, and determines and performs an action based on the comparison of the weighted summation to the thresholds.
    Type: Grant
    Filed: October 8, 1996
    Date of Patent: May 11, 1999
    Assignee: International Business Machines Corporation
    Inventors: Edward Gretz, David Allan Hellenga, Richard Kevin Hill
  • Patent number: 5896538
    Abstract: The present invention is directed to a system and method for monitoring system performance by using a multi-phase approach. The first phase, referred to as the burst counting phase, utilizes a set of counters to identify calls and returns which are heavily used. In the second phase, referred to as the instrumentation phase, the performance characteristics of the "hot spots" are monitored through the use of hardware counters. In a symmetrical multi-processor embodiment, the performance profiler is active on all processors at the same time. Frequently executed code paths are identified in a manner that is minimally-intrusive to the system as a whole, and uses relatively little storage. The user may specify a threshold count, after which hardware monitoring begins, and the user may specify the type of hardware performance data collected. After both phases of the performance monitor are run, the data can be presented to the user in a variety of ways.
    Type: Grant
    Filed: November 26, 1996
    Date of Patent: April 20, 1999
    Assignee: International Business Machines Corporation
    Inventors: Geoffrey Owen Blandy, Maher Afif Saba, Robert John Urquhart
  • Patent number: 5887173
    Abstract: In editing a program, when a reference variable name of a predetermined program line is designated, a line variable i (its initial value is 1) and line information n are compared. If i.gtoreq.n, the processing is ended. If i<n, a check is made as to whether the line i is a variable definition area. If the line i is not the variable definition area, the line variable i is incremented and the process is repeated. If the line i is the variable definition area, the line i is searched for the reference variable name. If the reference variable name is not found, the line variable i is incremented and then the process is repeated. If the reference variable name is found, the line information and the text information are stored in an INSERT buffer 23-5. The pieces of information are stored in a variable definition table 51 in an order of reception. Finally, the variable definition statement stored in the variable definition table 51 is displayed.
    Type: Grant
    Filed: August 18, 1995
    Date of Patent: March 23, 1999
    Assignee: Canon Kabushiki Kaisha
    Inventors: Yasuyuki Ogawa, Tsuneaki Kadosawa, Takashi Nakamura, Hitoshi Watanabe, Satoshi Asada