Abstract: Data processing apparatus comprises a processor and memory. The processor has a supervisor state including a first set of supervisor service routines for controlling the operation of the data processing apparatus. The memory has a first hash table accessible by the supervisor state for pointing to the first set of supervisor service routines and a second hash table also accessible by the supervisor state for pointing to a second set of supervisor service routines. The data processing apparatus provides table indicating means for indicating whether the first hash table or the second hash table is accessible by the supervisor state. The table indicating means is provided as an index into the first hash table. When this index is accessed, further code is executed which allows access to the second hash table.
Type:
Grant
Filed:
February 13, 1995
Date of Patent:
February 3, 1998
Assignee:
International Business Machines Corporation
Inventors:
Karl-Hans Holder, Ingolf Salm, Otto Weiss
Abstract: An apparatus and method for altering the configuration of a data processing system with a plurality of processors connected in a cluster or sysplex. On one of the processors, a TSO address space with modules for defining the configuration is started. These modules are able to request details of the input/output configuration datasets (IOCDS) stored on the other processors within the cluster, amend the information and return it to the other processors where it is available for use.
Type:
Grant
Filed:
March 28, 1995
Date of Patent:
January 27, 1998
Assignee:
International Business Machines Corporation
Inventors:
Charles W. Gainey, Matthias Gubitz, Harvey McGee, Charles E. Shapley, Robert A. Smith, Werner Wicke
Abstract: An optimizing compiler process and apparatus is disclosed for more accurately and efficiently identifying live variable sets in a portion of a target computer program, so as to more efficiently allocate registers in a computer central processing unit. The process of the invention includes the steps of performing a static single assignment transform to a computer program, including the addition of phi functions to a control flow graph. Basic blocks representing a use of a variable are further added to the control flow graph between the phi functions and definitions of the variables converging at the phi functions. A backward dataflow analysis is then performed to identify the live variable sets. The variables in the argument of phi functions are not included as a use of those variables in this dataflow analysis. The dataflow analysis may be iteratively performed until the live variable sets remain constant between iterations.
Abstract: A development system having a compiler that allows programmers and software developers to more efficiently develop compiled applications with runtime exception handling support is described. The compiler implements methods for handling of exceptions, which may occur during runtime execution of the program. In an exemplary embodiment, the system of the present invention registers exception handling information (e.g., an Exception Registration Record) with the underlying operating system, during execution of prolog code for each function (or other discrete section of code). The method is implemented so that the Exception Registration Record (ERR) resides at the bottom of the stack (or top of stack, for stack-based systems whose system stack grows upward) so that the information is positioned at one end of the stack during execution of the function.