Abstract: A selective oxidation process includes conducting a former phase of an oxidation process employing a thick mask layer to produce an oxide layer having a thickness less than the finished thickness of a desired semiconductor device isolation insulator. Then the thickness of the mask layer is reduced and a latter phase of the oxidation process using the reducing thickness mask layer is performed to produce the desired semiconductor device isolation insulator having the ultimate thickness. The use of both a thick mask layer and a reduced thickness mask layer for various phases of the oxidation process limits both the growth of the bird's beak and the growth of crystalline defects in the bird's beak.

Abstract: An electronic package comprising an integrated circuit chip and a flip chip solder bonded thereto is provided. The integrated circuit chip has circuitry over a major surface thereof and has peripheral wire or tab bond pads surrounding an array of C4 connection pads located over this major surface. A flip chip is solder bonded to the C4 connection pads.

Abstract: The testing of integrated circuits in a plurality of dice arranged in rows and columns in a semiconductor wafer is facilitated by effectively increasing the pitch between adjacent input/output bonding pads on each die by providing a plurality of test pads in scribing space between adjacent die. Alternate test pads are connected with alternate bonding pads on adjacent die, thereby effectively increasing the pitch of adjacent die for testing. After the integrated circuits are tested and defective circuits are marked, the wafer is scribed in the scribe space and broken to recover the individual die or integrated circuit chips.

Abstract: A method for forming a storage capacitor within an integrated circuit cell. There is first formed upon a semiconductor substrate an integrated circuit cell. The integrated circuit cell has formed therein a Field Effect Transistor (FET) which has an exposed source/drain electrode. The semiconductor substrate also has formed therein at least one other integrated circuit device which has at least one exposed contact electrode. There is then formed upon the semiconductor substrate a blanket conductor layer. The blanket conductor layer is then patterned to form a first portion of the blanket conductor layer and a second portion of the blanket conductor layer separate from each other. The first portion of the blanket conductor layer forms a patterned conductor layer contacting the exposed contact electrode of the other integrated circuit device.

Abstract: Conductive links are provided between conductive materials, e.g., metals, separated by a non-conductive material, e.g., a silicon-based glass material. In a preferred embodiment, a single pulse of laser energy is applied to at least one of the conductive materials to produce mechanical strain therein which strain initiates a fracturing of the non-conductive material so as to provide at least one fissure therein extending between the conductive materials. The laser energy pulse further causes at least one of the conductive materials to flow in such fissure to provide a conductive link between the conductive materials. Preferably, the non-conductive material is formed in layers such that an interface between the layers controls the fissures.

Abstract: A semiconductor memory device including a semiconductor substrate having a trench; a dielectric film formed on the substrate; a storage node electrode formed on the dielectric film; a first insulating film formed on the storage node electrode corresponding to the trench; a gate electrode formed on the first insulating film; a second insulating film formed on the gate electrode; a gate insulating film formed on at least one the side of gate electrode; a semiconductor layer formed on the at least one side of the first and second insulating films; and impurity regions formed in the semiconductor layer at the sides of the first and second insulating films.

Abstract: A titanium film is formed in a contact hole defined in a silicon substrate. The titanium film is transformed into a titanium silicide film and a first titanium nitride film by high-temperature lamp anneal. Further, a second titanium nitride film is stacked on the first titanium nitride film. Conditions are applied under which the titanium nitride films are formed into a granular crystal of primarily a (200) orientation. Therefore, barrier characteristics of the titanium nitride films to silicon atoms is not compromised even in the case of a subsequent high-temperature thermal treatment.

Abstract: Different thicknesses of gate oxide can be formed on a single chip in a single oxidation process by selectively implanting nitrogen into the surface of the chip in a pattern corresponding to the desired differences in gate oxide thickness. Implanting nitrogen to a silicon substrate reduces the rate at which oxide grows on the surface. Thus, by implanting different dosages of nitrogen into the surface of the substrate, thicker or thinner oxide layers can be provided. A processing chip with embedded DRAM can then be formed where the logic circuitry has a thin gate oxide and the DRAM circuitry has a thick gate oxide by implanting the higher dosage of nitrogen into the region of the chip where the logic circuits are to be formed. Different gate oxide thicknesses are then provided by exposing both the logic circuitry and the embedded DRAM section to a single thermal oxidation process.

Abstract: A packaged integrated circuit configured for interconnection to an external component comprises a die (1) having a high frequency contact (8), the die (1) being disposed on a lead frame (3). The lead frame (3) comprises a plurality of leads (9). At least two of the leads are first and second RF port leads (9a, 9b) which are electrically connected to the RF port. When mounted to a printed circuit board substrate, there is a capacitor (12) connected between the first and second high frequency contact (8) leads (9a, 9b) to achieve frequency specific signal attenuation at an unwanted frequency with minimal contribution of insertion loss at a desired frequency.

Abstract: A method of forming a narrow space using a litho-less process is disclosed. A first mask is formed on a substrate, the first mask having an edge. A spacer is then formed adjacent to the edge. A second mask is subsequently formed adjacent to the spacer. The spacer is then removed.

Abstract: A gate array is disclosed having a programmable polysilicon layer which serves as both the gate electrodes for MOS transistors and routing lines for some connections between gate electrodes. The gate array structure is formed on a semiconductor substrate and has an array of identical base cells located in a core region of the structure. Each such base cell des the following elements: (1) a plurality of transistors, each of which includes a gate electrode; and (2) one or more gate connection strips formed on the substrate and electrically connecting selected gate electrodes of two or more of the transistors. Preferably, the gate connection strips are made from the same material as the selected gate electrodes (e.g., polysilicon) and are integrally connected therewith. The gate connection strips may patterned (i.e., programmed) to form substrate level routing between gates of various transistors.

Abstract: A method for forming a dynamic random access memory device includes the step of forming a memory cell access transistor on a semiconductor substrate wherein the memory cell access transistor includes a source/drain region at a surface of the semiconductor substrate. An insulating layer is formed on the semiconductor substrate and on the memory cell access transistor wherein the insulating layer has a contact hole therein exposing a portion of the source/drain region of the substrate. A first conductive layer is chemical vapor deposited on the exposed portion of the source/drain region of the substrate, and a second conductive layer is physical vapor deposited on the first conductive layer opposite the substrate. A dielectric layer is formed on the second conductive layer opposite the substrate, and a third conductive layer is formed on the dielectric layer opposite the substrate.

Abstract: Power consumption in a liquid crystal display driver is reduced without degrading display quality of a liquid crystal display. Supply of unnecessary oscillation voltage to the liquid crystal display is stopped by turning off all analog switches AS.sub.0 -AS.sub.7 under the control of a signal TI at the moment when voltage applied to the liquid crystal display reaches a desired DC voltage corresponding to display data D.sub.0 -D.sub.2.

Abstract: A method for forming an integrated circuit device includes the steps of forming a first capacitor electrode on a substrate and forming a first wiring electrode on the substrate. An insulating layer is formed on the first capacitor electrode and on the first wiring electrode opposite the substrate. A second capacitor electrode is formed on a portion of the insulating layer opposite the first capacitor electrode. A contact hole is formed in the insulating layer exposing a portion of the first wiring electrode. A second wiring electrode is then formed on the exposed portion of the wiring electrode, after forming the second capacitor electrode. Related structures are also discussed.

Abstract: A mount 2 is secured on a circuit board 1 to support a diode chip 3 thereon. A plurality of legs 7, 12 formed in the mount 2 are in contact with an electrode 4 on the circuit board 1 to form at least a dent 14. The mount 2 also has an inclined surface 8 formed at the periphery which faces the electrode 4. Solder 9 is filled in the dent 14 between the legs 7, 12 and in the flaring area 13 between the circuit board 1 and the inclined surface 8 of the mount 2 to prevent exfoliation or detachment of the mount from the electrode 4.

Abstract: The invention relates to a multilayer module 20 for packaging of at least one electronic component, such as the integrated circuit chips 21, 22. The module 20 comprises a thickfilm structure and a thinfilm structure. The thinfilm structure provides an interface between the electronic components and the thickfilm structure. The thinfilm structure comprises a first powerplane and a redistribution wiring structure. The topmost layer of conductors of the thickfilm structure is a second powerplane so that an electrical structure approaching a triplate structure is realized.

Abstract: An insulated gate thyristor is provided in which an inversion layer is created beneath a gate electrode to which a voltage is applied. An emitter region of a first conductivity type is biased to the same potential as a first main electrode via a MOSFET channel, and a thyristor portion consisting of the emitter region, a second base region of a second conductivity type, a base layer of the first conductivity type and an emitter layer of the second conductivity type is turned on. As electrons are injected uniformly from the entire emitter region, the insulated gate thyristor quickly shifts to the thyristor mode, and the on-voltage of the insulated gate thyristor of the invention is lowered. The insulated gate thyristor of the invention does not require a hole current that flows through the second base region of a convention EST in the Z-direction. In turning off, the pn junction recovers quickly without causing current localization, and the breakdown withstand capability if improved.

Abstract: In a semiconductor device manufacturing method for forming first and second bipolar transistors on a semiconductor substrate 1, a link base layer 5 for connecting a graft base layer (graft base layer 8) of the first bipolar transistor and an intrinsic base layer 12 to each other, and at least a part of a base layer 6 of the second bipolar transistor are formed simultaneously with each other, and then the link base layer 5 in a region where the intrinsic base layer 12 will be formed is removed by an etching treatment, and then by a selective epitaxial growth method, the intrinsic base layer 12 is formed in the region where the link base layer 5 is removed.

Abstract: A semiconductor device, which has an oxide laver with the thickness thereof being varied from portion to portion of the inner surface of a trench and can be easily produced, and a process of producing the same. An n.sup.+ type single crystal SiC substrate is formed of SiC of hexagonal system having a carbon face with a (0001) face orientation as a surface, and an n type epitaxial layer and a p type epitaxial layer are successively laminated onto the substrate. An n.sup.+ source region is provided within the p type epitaxial layer, and the trench extends through the source region and the epitaxial layer into the semiconductor substrate. The side face of the trench is almost perpendicular to the surface of the epitaxial layer with the bottom face of the trench having a plane parallel to the surface of the epitaxial layer. The thickness of a gate oxide layer, formed by thermal oxidation, on the bottom face of the trench is larger than the thickness of the gate oxide layer on the side face of the trench.

Abstract: A semiconductor device includes a wiring board having a main surface and a plurality of pad electrodes formed on the main surface, a rectangular semiconductor element having a main surface facing the main surface of the wiring board and mounted on the main surface of the wiring board, a solder resist formed to surround the semiconductor element with a preset distance therefrom on the main surface of the wiring board, a plurality of terminal electrodes formed on the end portion of the main surface of the semiconductor element, and a plurality of solder bumps for electrically connecting the plurality of pad electrodes to the plurality of terminal electrodes with a gap provided between the main surface of the wiring board and the main surface of the semiconductor element, wherein each of the plurality of pad electrodes includes at least a portion which extends from substantially under a corresponding one of the plurality of terminal electrodes of the semiconductor element to the solder resist lying outside the s