Abstract: A method for fabricating a CMOS device having BILLI (buried implanted layers for lateral isolation) structure capable of effectively preventing latch-up is disclosed, having the following steps. A mask pattern is formed on the semiconductor substrate of a predetermined conductivity type to expose a region where the MOS transistor, having a same conductivity type as that of the substrate, is to be formed wherein the mask pattern has a vertical boundary face having a gradual slope. A buried layer is then formed in the form of island by ion-implanting the impurity ions into the substrate to pass through the mask pattern, the buried layer having a same conductivity type as that of the substrate, and being formed to be continuous under the vertical boundary face of the mask pattern.

Abstract: Laser anneal processing of a semiconductor layer is repeated in a number of steps. Grain size is increased using high energy ELA for a first step, and grain sizes are uniformed using ELA with low energy for a later step. As a defective crystallization region occurs in an excessive energy region during the ELA for the first step, in the ELA for the second time, excessive energy is removed and the defective crystallization region is eliminated by reducing the energy to an optimal value, thereby improving the crystallinity of a p-Si layer.

Abstract: A dielectric pattern. On a substrate having a metal wiring layer formed thereon, a first dielectric layer and a first masking layer are formed. A cap insulation layer is formed on the masking layer. The first dielectric layer, the first masking layer and the cap insulation layer are penetrated through by a first opening. A second dielectric layer and a second masking layer are formed on the cap insulation layer. The second dielectric layer and the second masking layer are penetrated through by a second opening. The first and the second openings are contiguous without intermittence.

Abstract: A contact (26) to a substrate (12) is formed using a first stopping layer (14), an insulating layer (16), and a second stopping layer (18). The second stopping layer (18) promotes a more accurate and controlled removal of the first stopping layer (14). A self-aligned contact (122) may be formed in a similar manner using a first stopping layer (110), an insulating layer (112), and a second stopping layer (114).

Abstract: A semiconductor device comprising a wiring circuit board and a semiconductor chip mounted through a bump electrode on the circuit board, a space between the circuit board and the semiconductor chip as well as a periphery of the semiconductor chip being encapsulated with a resin containing a filler. The resin is constituted by a first resin disposed in a region surrounded by bump electrodes positioned on the outermost periphery of the semiconductor chip, and by a second resin disposed in a region not surrounded by bump electrodes positioned on the outermost periphery of the semiconductor chip, the first and second resins being distinct from each other in at least one feature selected from a content, a maximum particle diameter and an average particle diameter of the filler.

Abstract: A hetero junction type field effect transistor can control a short channel effect, reduce the fluctuation of a threshold, and improve a yield. The hetero junction type field effect transistor comprises: a semiconductor substrate, a first electron feed layer made of a doped semiconductor having a wider band gap than the channel layer, a channel layer made of a non-doped semiconductor, a second electron feed layer comprising a laminate structure of a plurality of semiconductor layers having a wider band gap than the channel layer and having a thickness of 100 .ANG. or less, and a gate electrode, a source electrode, and a drain electrode.

Abstract: A distributed feedback semiconductor laser which includes a semiconductor substrate of a first conductive type; a semiconductor multi-layer structure provided on the semiconductor substrate and including an active layer for generating laser light; and a gain-coupled diffraction grating provided between the semiconductor substrate and the semiconductor multi-layer structure. The diffraction grating includes a plurality of curved projections periodically arranged at a surface of the semiconductor substrate and a quantum well light absorption layer for covering the plurality of curved projections. The quantum well light absorption layer includes a light absorption area having a first thickness at each border between two adjacent curved projections and a non-light absorption area having a second thickness which is smaller than the first thickness at a top of each of the curved projections.

Abstract: A method of manufacturing a joined-type semiconductor device having a gate structure. The semiconductor device includes a first and second semiconductor substrates each having a substrate body, and a first and a second main surfaces which are opposite to each other. A gate structure is formed in the first main surface of the first substrate. A highly-doped semiconductor layer is formed in the first main surface of the second substrate and has an impurity-concentration which is higher than that of the substrate body of the second substrate. The first main surfaces of the two substrates are joined with each other, by subjecting the two substrates to a heat treatment so that impurities in the highly-doped semiconductor layer of the second substrate are driven into the surface region of the first substrate, and a diffusion layer is thereby formed in the first main surface of the first substrate.

Abstract: A method of making N-channel and P-channel devices using separate drive-in steps is disclosed. The method includes providing a semiconductor substrate with first and second active regions, introducing a first dopant into the first active region to provide all doping for a source and a drain in the first active region, driving-in the first dopant to form the source and the drain in the first active region, introducing a second dopant into the second active region to provide all doping for a source and a drain in the second active region after driving-in the first dopant, and driving-in the second dopant to form the source and the drain in the second active region. Preferably, the first dopant is arsenic or phosphorus, the second dopant is boron, and the first temperature exceeds the second temperature by at least 50.degree. C. In this manner, the boron need not be subjected to the higher first temperature, thereby reducing boron diffusion.

Abstract: A method of selectively and simultaneously depositing a non-reactive material such as a polyimide polymer to vertical sidewalls of a mesa-like structure is provided. The method of the present invention is useful in providing a modified mesa-like structure which prevents the flow of a reactive material along the vertical sidewalls of the mesa-like structure.

Abstract: The present invention includes forming gate structures having a nitride cap on the substrate. An ion implantation is used to dope ions into the substrate to form the lightly doped drain (LDD) structures. An oxide layer is formed on the gate structures. Subsequently, the oxide layer is etched back to form oxide spacers on the side walls of the gate structures. Next, an ion implantation with a high dose is carried out to dope nitrogen ions into the oxide spacers, the cap silicon nitride and the silicon substrate. The cap silicon nitride layer is then removed. Then, a refractory or noble metal layer is sputtered on the substrate, nitride doped oxide spacers and the gates. A first step thermal process is performed to form SALICIDE and polycide. Next, an ion implantation is utilized to dope ions into the SALICIDE and polycide films. A second step thermal process is employed to form shallow source and drain junction.

Abstract: A method of fabricating a liquid crystal display device having a substrate includes the steps of forming a gate electrode on the substrate, forming a gate insulating layer on the gate electrode, forming a semiconductor layer on the gate insulating layer, forming source/drain electrodes on the semiconductor layer, forming a pixel electrode on the source/drain electrodes including the gate insulating layer, forming a passivation layer on the pixel electrode including the source/drain electrodes, forming a light shielding layer on the passivation layer, forming an alignment layer on the light shielding layer including the passivation layer, and determining an alignment direction by exposing the alignment layer to a light.

Abstract: A CMOS semiconductor device is formed having an N-channel transistor comprising a graded junction with reduced junction capacitance. The graded junction is achieved by forming a second sidewall spacer on the gate electrode, after source/drain implantations, and ion-implanting an N-type impurity with high diffusivity, e.g., P into an A.sub.5 implant, followed by activation annealing.

Abstract: A solder interconnection uses preferably lead-rich balls for making a low temperature chip attachment directly to any of the higher levels of packaging substrate. After a solder ball has been formed using standard processes, a ball limiting metal mask is formed using photoresist. A thin cap layer of preferably pure tin is deposited on a surface of the solder balls using a tin aqueous immersion process.

Abstract: A fabrication sequence of a thin film transistor, in which a photoresist film is used as an ion doping mask to shield a portion of an amorphous semiconductor layer larger than a gate electrode formed above in width (gate length). The mask is designed by pre-calculating the accuracy of the alignment and etching, so that the gate electrode overlaps neither the source region nor drain region. Thus, it has become possible to form the gate electrode in such a manner not to overlap the source region or drain region while securing an impurity-free offset region. As a result, the present thin film transistor can reduce the OFF-state current and renders excellent OFF-state characteristics, and therefore, when employed in a liquid crystal display device, the resulting liquid crystal display device can prevent display defects, such as a flicker.

Abstract: The manufacturing processes can be simplified and the reliability can be improved. A method of processing a thin film includes a first process of selectively forming a resist pattern on a ground surface, a second process of forming a thin film on the ground surface and a surface of the resist pattern, and a third process of removing the resist pattern to selectively remove the thin film deposited on the former, i.e., carrying out the lift-off, thereby the thin film process for a desired pattern being carried out.

Abstract: Of ends of a plurality of inner leads disposed around a semiconductor chip shaped substantially in the form of a rectangle, the ends of the inner leads, which correspond to the corners of the rectangle, are provided so as to approach in the direction of the semiconductor chip. Owing to the provision referred to above, bonding wires for connecting electrical connections between the semiconductor chip and the ends of the inner leads can be prevented from drifting upon a mold process.

Abstract: The bending of a ball grid array electronic package having a metallic base is reduced minimizing stresses applied to the innermost row of solder balls when the package base is cyclically heated and cooled. Reducing the stresses applied to the solder balls increases the number of thermal cycles before solder ball fracture causes device failure. Among the means disclosed to reduce the bending moment are a bimetallic composite base, an integral stiffener, a centrally disposed cover bonded to an external structure and a package base with a stress accommodating depressed portion.

Abstract: A semiconductor device having a protection layer covering the active layer of a semiconductor chip with an opening therein corresponding in location to a chip electrode located on the active surface of the semiconductor chip. Inside the opening a barrier layer covers the chip electrode, a diffusion barrier layer covers the barrier layer and a protruding contact protruding from the diffusion barrier layer. The protruding contact preferably comprises material whose hardness is lower than that of each of the barrier layer and chip electrode.

Abstract: A method of forming a capacitor for a semiconductor memory device, includes the steps of forming first and second insulating layers to form a first contact hole on a substrate, forming a first conductive layer and a third insulating layer within the first contact hole so as to define a second contact hole, forming a second conductive layer within the second contact hole, removing the second and third insulating layers to form a storage electrode, and forming a dielectric layer and a third conductive layer on the storage electrode to form a capacitor.