Patents Examined by Phallaka Kik
  • Patent number: 11907627
    Abstract: In an integrated circuit (IC) assessment method, an artificial intelligence (AI) component comprising at least one artificial neural network (ANN) is trained to transform layout rendering tiles of a rendering of a reference IC into corresponding reference layout image tiles extracted from at least one layout image of the reference IC. Using the trained AI component, standard cell layout renderings of a library of GDSII or OASIS standard cell layout renderings are transformed into as-fabricated standard cell layout renderings forming a library of as fabricated standard cell layout renderings. Instantiated standard cells and their placements in the layout image of an IC-under-test are identified by matching the instantiated standard cells with corresponding as-fabricated standard cell layout renderings retrieved from the library of as fabricated standard cell layout renderings.
    Type: Grant
    Filed: December 8, 2021
    Date of Patent: February 20, 2024
    Assignee: BATTELLE MEMORIAL INSTITUTE
    Inventors: Adam Kimura, Rohan Prabhu, Noah Mun
  • Patent number: 11897348
    Abstract: A power transmission device that wirelessly transmits power to a vehicle, the power transmission device including an information emitter that, in a case in which the position of the vehicle acquired by the information acquirer is located in a power transmission range of the power transmission coil and, also, the instruction receiver receives the instruction about power transmission, emits a first type of information that indicates a presence of the foreign object when the detector detects the foreign object, and in a case in which the instruction receiver does not receive the instruction about power transmission even though the position of the vehicle acquired by the position information acquirer is located in the power transmission range of the power transmission coil, does not emit the information that indicates the presence of the foreign object.
    Type: Grant
    Filed: July 1, 2021
    Date of Patent: February 13, 2024
    Assignee: TDK CORPORATION
    Inventor: Akira Gotani
  • Patent number: 11901759
    Abstract: A method of developing a charging profile for charging a lithium-ion battery. A first phase of charging is at a constant current level, with the constant current level selected on the basis of battery resistance during charging and differential voltage (dV/dQ) analysis. A switch point is selected on the basis of a state of charge (SOC) of the battery when dV/DQ values increase. Next is an increasing voltage charging phase, with the voltage rate selected on the basis of charge acceptance and charge time.
    Type: Grant
    Filed: July 16, 2021
    Date of Patent: February 13, 2024
    Assignee: Southwest Research Institute
    Inventors: Bapiraju Surampudi, Shuvodeep Bhattacharjya, Kevin Jones
  • Patent number: 11892518
    Abstract: A method of operating a control device includes performing an open load test or a current leakage test. The open load test includes activating a first current and then a second current and sensing with the first current and the second current activated, respectively, a first voltage drop and a second voltage drop between charge distribution pins and charge sensing pins of the control device. Respective differences are calculated between the first voltage drop and the second voltage drop sensed with the first current and the second current activated, respectively. These differences are compared with respective thresholds and an open circuit condition is declared as a result of the differences calculated reaching these thresholds.
    Type: Grant
    Filed: July 6, 2021
    Date of Patent: February 6, 2024
    Assignee: STMicroelectronics S.r.l.
    Inventors: Orazio Pennisi, Valerio Bendotti, Vanni Poletto, Vittorio D'Angelo
  • Patent number: 11874323
    Abstract: Disclosed is a JTAG-based burning device, including controllable switches arranged between a TDI terminal of a JTAG host and a first chip, and between two adjacent chips, and further including a master controllable switch module arranged between each chip and a TDO terminal of the JTAG host, wherein the JTAG host may, according to a received burning instruction, control corresponding input terminals of the controllable switches to be connected to corresponding output terminals and also control an output terminal of the master controllable switch module to be connected to the corresponding input terminal. Obviously, a JTAG chain can be automatically adjusted by controlling the connection relationship between input and output terminals of the corresponding switches by only building a circuit, so that firmware burning on different chips or chip combinations is realized without manual adjustment, thereby improving the test efficiency, and simplifying the circuit structure.
    Type: Grant
    Filed: September 27, 2019
    Date of Patent: January 16, 2024
    Assignee: Inspur Suzhou Intelligent Technology Co., Ltd.
    Inventor: Peng Wang
  • Patent number: 11876383
    Abstract: A wireless charging system having a power transmitting device may wirelessly transfer power to a power receiving device. The power receiving device may include a voltage regulator that operates independently from the power transmitting device. The voltage regulator may output a rectified voltage and may activate pull-down rectifier switches during zero voltage crossings to boost the rectified voltage. The power receiving device may send control error packets to the power transmitting device to direct the power transmitting device to adjust the transmit power level.
    Type: Grant
    Filed: May 6, 2021
    Date of Patent: January 16, 2024
    Assignee: Apple Inc.
    Inventor: Alireza Safaee
  • Patent number: 11868692
    Abstract: Address generators for use in verifying an integrated circuit hardware design for an n-way set associative cache. The address generator is configured to generate, from a reverse hashing algorithm matching the hashing algorithm used by the n-way set associative cache, a list of cache set addresses that comprises one or more addresses of the main memory corresponding to each of one or more target sets of the n-way set associative cache. The address generator receives requests for addresses of main memory from a driver to be used to generate stimuli for testing an instantiation of the integrated circuit hardware design for the n-way set associative cache. In response to receiving a request the address generator provides an address from the list of cache set addresses.
    Type: Grant
    Filed: April 2, 2021
    Date of Patent: January 9, 2024
    Assignee: Imagination Technologies Limited
    Inventors: Anthony Wood, Philip Chambers
  • Patent number: 11862999
    Abstract: An online reconfigurable battery system with current surge protection modules (SPM), including: a plurality of battery module strings connected in parallel. The battery module string further includes: an SPM and a plurality of enable/bypass battery modules (EBM) connected in series; where the EBM further includes: a battery, a first switch, and a second switch; the first switch and the battery are connected in series, and then connected to the second switch in parallel to form an EBM that can be enabled or bypassed; the SPM further includes: a variable resistor, a third switch, and a fourth switch; the third switch and the variable resistors are connected in series, and then connected in parallel with the fourth switch to buffer the surge current.
    Type: Grant
    Filed: August 2, 2021
    Date of Patent: January 2, 2024
    Assignee: FORTUNE ELECTRIC CO., LTD.
    Inventors: Shou-Hung Welkin Ling, Jui-Yang Tsai, Jason S. Lin, I-Sheng Hsu
  • Patent number: 11847392
    Abstract: An approach is disclosed herein for dynamic design switching for high performance mixed signal simulation. Disclosed herein is a new approach to simulation processes that allows for different segments of a design to be swapped out without requiring re-elaboration. This is an improvement over current techniques and decreases the amount of time need to simulate a design. In some embodiments, the technique illustrated herein is combined with an automated triggering mechanism that controls the selection of alternate representations for the same element base on those triggers. In some embodiments a new multiplexor structure is provided that is specifically tailored to solving the present issue.
    Type: Grant
    Filed: November 30, 2021
    Date of Patent: December 19, 2023
    Assignee: Cadence Design Systems, Inc.
    Inventors: Qingyu Lin, Patrick O'Halloran, Xiao Wang
  • Patent number: 11847394
    Abstract: A system and method for adding interface protection to an electronic design using parameters. The electronic design and interface protection scheme are defined as parameters. An interface protection model creates interface protection implementation parameters that describe the implementation details of the interface protection. A hardware description model uses the electronic design parameters and the interface protection implementation parameters to create a hardware description. The interface protection scheme can be a built-in protection scheme, a user defined scheme, a scheme that includes place holders that the user may define later, and a combination of the preceding. The interface protection scheme may contain components to help with the retiming of the description of hardware.
    Type: Grant
    Filed: December 2, 2021
    Date of Patent: December 19, 2023
    Assignee: Arteris, Inc.
    Inventors: John Coddington, Sylvain Meliciani, Frederic Greus, Xavier Van Ruymbeke
  • Patent number: 11847393
    Abstract: A computing device, method and computer program product are provided in order to develop a system model. In a method, a simulation model is designed that is configured to digitally simulate a corresponding portion of a system. The method also includes associating a simulation assessment module with the simulation model. The simulation assessment module is configured to verify one or more signals propagating within the simulation model. In an instance in which the simulation assessment module has verified the one or more signals, the method includes performing a unit test upon the simulation model to confirm proper operation of the simulation model. In an instance in which the unit test is successful, the method includes integrating a plurality of simulation models to form the system model.
    Type: Grant
    Filed: December 16, 2021
    Date of Patent: December 19, 2023
    Assignee: THE BOEING COMPANY
    Inventors: Bruno J. Correia GrĂ¡cio, Daniel Ramiro Rebollo, Pieter Van Gils
  • Patent number: 11837891
    Abstract: The present invention relates a modular charging system including a wall mounted outlet preserving charger and charging additional accessories, such as battery blocks, wireless device chargers, supporting chargers for wearable devices such as watches, and car chargers, each for use independently or in combination with electronic devices. The present invention typically includes a wall charger with one or more electrical outlets on the front face so that the use of the wall outlet is not lost. The wall charger of the present invention is suitable for use in any major country and may be adapted to the outlet configuration and voltage of those countries.
    Type: Grant
    Filed: October 6, 2022
    Date of Patent: December 5, 2023
    Assignee: Mischievous LLC
    Inventor: Seymour Segnit
  • Patent number: 11836575
    Abstract: Methods, systems and apparatus for approximating a target quantum state. In one aspect, a method for determining a target quantum state includes the actions of receiving data representing a target quantum state of a quantum system as a result of applying a quantum circuit to an initial quantum state of the quantum system; determining an approximate quantum circuit that approximates the specific quantum circuit by adaptively adjusting a number of T gates available to the specific quantum circuit; and applying the determined approximate quantum circuit to the initial quantum state to obtain an approximation of the target quantum state.
    Type: Grant
    Filed: September 25, 2018
    Date of Patent: December 5, 2023
    Assignee: Google LLC
    Inventors: Ryan Babbush, Austin Greig Fowler
  • Patent number: 11816412
    Abstract: A method of forming an integrated circuit structure is provided. The method includes: providing a logic cell structure including a first input node, a second input node, and a pulling network connected to a reference voltage and an output node, wherein the pulling network includes a plurality of transistor segments; determining a delay associated with at least one of the first input node and the second input node; and connecting the plurality of transistor segments to the first input node, the second input node and the output node based at least in part on the determined delay.
    Type: Grant
    Filed: April 16, 2021
    Date of Patent: November 14, 2023
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.
    Inventors: Kumar Lalgudi, Ranjith Kumar, Mohammed Rabiul Islam, Jianyang Xu
  • Patent number: 11797735
    Abstract: A method of testing a product using confidence estimates is provided. The method includes identifying a set of candidate tests and estimating a respective confidence score for each candidate test, the confidence scores reflecting a level of confidence that the corresponding candidate tests will pass or fail when being performed on the product, the estimating including determining the respective confidence scores in dependence upon at least one of (i) previously obtained test results, (ii) changes to the product since a previous estimation or regression test has been performed and (iii) information regarding a user. The method includes identifying a candidate test having a confidence score that is below a threshold, in response to the identification of the candidate test, performing the candidate test, and providing, to a user, results of the performing of the candidate test.
    Type: Grant
    Filed: March 5, 2021
    Date of Patent: October 24, 2023
    Assignee: Synopsys, Inc.
    Inventors: Boris Gommershtadt, Leonid Greenberg, Ilya Kudryavtsev, Yaron Shkedi
  • Patent number: 11797742
    Abstract: A method includes: receiving a representation of a mixed-signal integrated circuit design including an analog circuit portion and a digital circuit portion including a plurality of descriptions of a power supply, the descriptions including a power supply network description and a register transfer level (RTL) hardware description language (HDL) description; determining a mismatch between the power supply network description and the HDL description of the power supply; generating a value converter to convert a voltage value associated with the power supply between the power supply network description and the HDL description; and converting, by a processor, between the power supply network description and the HDL description during runtime using the value converter to synchronize the power supply network description and the HDL description of the power supply responsive to the mismatch.
    Type: Grant
    Filed: December 22, 2021
    Date of Patent: October 24, 2023
    Assignee: SYNOPSYS, INC.
    Inventors: Diganchal Chakraborty, Jiri Prevratil, Harsh Chilwal, Shreedhar Ramachandra, Prasenjit Biswas
  • Patent number: 11775722
    Abstract: Systems and methods for generating an integrated circuit (IC) chip design are described. One of the methods includes receiving, on a data sheet, by a server, electrical parameters of a system on chip (SoC) to be designed. The method further includes receiving physical parameters of the SoC on the data sheet, generating a first design of the SoC according to the electrical parameters and the physical parameters, and receiving test parameters for testing the first design. The method further includes testing, via a design verification tool, the first design by applying the test parameters to the first design, receiving a second design of a second SoC, and coupling the second design to the first design to generate a first IC chip design. The method includes arranging the first IC chip design to be included on a shuttle for fabricating a first IC chip.
    Type: Grant
    Filed: October 4, 2021
    Date of Patent: October 3, 2023
    Assignee: efabless corporation
    Inventors: Bertrand Irissou, John M. Hughes, Lucio Lanza, Mohamed K. Kassem, Michael S. Wishart, Rajeev Srivastava, Risto Bell, Robert Timothy Edwards, Sherif Eid, Greg P. Shaurette
  • Patent number: 11775725
    Abstract: A system includes a processor configured to determine a power parameter associated with a cell in an integrated circuit (IC) layout diagram. In response to the determined power parameter exceeding a design criterion, the processor is configured to perform a modification of the IC layout diagram, the modification including at least one of altering a placement of the cell in the IC layout diagram or modifying a power delivery path to the cell. The power parameter includes at least one of a power density of a tile containing the cell, a voltage drop of the tile containing the cell, or a voltage drop of the cell.
    Type: Grant
    Filed: November 16, 2021
    Date of Patent: October 3, 2023
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Chin-Shen Lin, Hiranmay Biswas, Kuo-Nan Yang, Chung-Hsing Wang
  • Patent number: 11775718
    Abstract: Methods, apparatus, systems and articles of manufacture are disclosed to simulate metastability for circuit design verification. An example apparatus includes an input handler to receive circuit design data indicative of a circuit design, a circuit modeler to generate a simulation model based on the circuit design data, a simulator to simulate operation of the circuit design based on the simulation model, a metastability injector to insert metastability logic into the simulation model during the simulation, and a metastability controller to control the metastability logic during the simulation.
    Type: Grant
    Filed: December 1, 2022
    Date of Patent: October 3, 2023
    Assignee: TEXAS INSTRUMENTS INCORPORATED
    Inventors: Sudhakar Surendran, Venkatraman Ramakrishnan
  • Patent number: 11775715
    Abstract: Disclosed is a method of operating a system-on-chip automatic design device. The system-on-chip automatic design device includes a first synthesizer and a second synthesizer. The method includes generating a first code, based on information of a first signal and information of a second signal that are used in a first IP (Intellectual Property) block, classifying a first signal code corresponding to the first signal and a second signal code corresponding to the second signal from the first code, synthesizing, through the first synthesizer, a first communication architecture configured to transmit the first signal, based on the classified first signal code, and synthesizing, through the second synthesizer, a second communication architecture configured to transmit the second signal based on the classified second signal code.
    Type: Grant
    Filed: December 9, 2020
    Date of Patent: October 3, 2023
    Assignee: ELECTRONICS AND TELECOMMUNICATIONS RESEARCH INSTITUTE
    Inventors: Kyuseung Han, Sukho Lee, Jae-Jin Lee