Patents Examined by Phat Cao
  • Patent number: 8212305
    Abstract: A semiconductor device having a nonvolatile memory is reduced in size. In an AND type flash memory having a plurality of nonvolatile memory cells having a plurality of first electrodes, a plurality of word lines crossing therewith, and a plurality of floating gate electrodes disposed at positions which respectively lie between the plurality of adjacent first electrodes and overlap the plurality of word lines, as seen in plan view, the plurality of floating gate electrodes are formed in a convex shape, as seen in cross section, so as to be higher than the first electrodes. As a result, even when nonvolatile memory cells are reduced in size, it is possible to process the floating gate electrodes with ease. In addition, it is possible to improve the coupling ratio between floating gate electrodes and control gate electrodes of the word lines without increasing the area occupied by the nonvolatile memory cells.
    Type: Grant
    Filed: December 9, 2009
    Date of Patent: July 3, 2012
    Assignee: Renesas Electronics Corporation
    Inventors: Tatsuya Fukumura, Yoshihiro Ikeda, Shunichi Narumi, Izumi Takesue
  • Patent number: 8133800
    Abstract: A method of fabricating a thickness of silicon material includes providing a silicon ingot material having a surface region and introducing a plurality of particles having an energy of about 1-5 MeV through the surface region to a depth to define a cleave region and a thickness of detachable material between the cleave region and the surface region. Additionally, the method includes processing the silicon ingot material to free the thickness of detachable material at a vicinity of the cleave region and causing formation of a free-standing thickness of material characterized by a carrier lifetime about 10 microseconds and a thickness ranging from about 20 microns to about 150 microns with a thickness variation of less than about five percent. Furthermore, the method includes treating the free-standing thickness of material using a thermal treatment process to recover the carrier lifetime to about 200 microseconds and greater.
    Type: Grant
    Filed: July 23, 2009
    Date of Patent: March 13, 2012
    Assignee: Silicon Genesis Corporation
    Inventors: Francois J. Henley, Sien Kang, Zuqin Liu, Lu Tian
  • Patent number: 8129820
    Abstract: A bipolar transistor for semiconductor device has a collector region having a first conductivity type disposed on a surface of a semiconductor substrate having the first conductivity type. A base region having a second conductivity type is disposed in the collector region. An emitter region having the first conductivity type is disposed in the base region. A high concentration first conductivity type region for a collector electrode is disposed in the collector region. A high concentration second conductivity type region for a base electrode is disposed in the base region. The high concentration first conductivity type region for a collector electrode and the high concentration second conductivity type region for a base electrode contact directly with each other so that the collector region and the base region have a same potential.
    Type: Grant
    Filed: August 27, 2008
    Date of Patent: March 6, 2012
    Assignee: Seiko Instruments Inc.
    Inventors: Hideo Yoshino, Hisashi Hasegawa
  • Patent number: 8124985
    Abstract: There are provided a nitride semiconductor light emitting device having a structure enabling enhanced external quantum efficiency by effectively taking out light which is apt to repeat total reflection within a semiconductor lamination portion and a substrate and attenuate, and a method for manufacturing the same. A semiconductor lamination portion (6) including a first conductivity type layer and a second conductivity type layer, made of nitride semiconductor, is provided on a surface of the substrate (1) made of, for example, sapphire or the like. A first electrode (for example, p-side electrode (8)) is provided electrically connected to the first conductivity type layer (for example, p-type layer (5)) on a surface side of the semiconductor lamination portion (6), and a second electrode (for example, n-side electrode (9)) is provided electrically connected to the second conductivity type layer (for example, n-type layer (3)).
    Type: Grant
    Filed: February 7, 2006
    Date of Patent: February 28, 2012
    Assignee: Rohm Co., Ltd.
    Inventors: Mitsuhiko Sakai, Atsushi Yamaguchi, Ken Nakahara, Masayuki Sonobe, Tsuyoshi Tsutsui
  • Patent number: 8114748
    Abstract: A method of forming a semiconductor device is provided that includes forming a gate structure atop a substrate and implanting dopants into the substrate to a depth of 10 nm or less from an upper surface of the substrate. In a following step, an anneal is performed with a peak temperature ranging from 1200° C. to 1400° C., and a hold time period ranging from 1 millisecond to 5 milliseconds.
    Type: Grant
    Filed: June 25, 2009
    Date of Patent: February 14, 2012
    Assignee: International Business Machines Corporation
    Inventors: Kam-Leung Lee, Paul A. Ronsheim
  • Patent number: 8105866
    Abstract: A semiconductor photo detecting element includes a PIN-type photo detecting element and window semiconductor layer. The PIN-type photo detecting element has a semiconductor substrate, a first semiconductor layer, a second semiconductor layer and a third semiconductor layer. The first semiconductor layer is provided on the semiconductor substrate, is lattice-matched to the semiconductor substrate, includes a first conductivity type dopant, and has first band gap energy. The second semiconductor layer is provided on the first semiconductor layer, has the first band gap energy, and has a concentration of the first conductivity type dopant lower than that of the first semiconductor layer or is substantially undoped. The third semiconductor layer is provided on the second semiconductor layer. The window semiconductor layer has second band gap energy larger than the first band gap energy at a light-incoming side with respect to the second semiconductor layer and has a thickness of 5 nm to 50 nm.
    Type: Grant
    Filed: February 24, 2010
    Date of Patent: January 31, 2012
    Assignee: Eudyna Devices Inc.
    Inventors: Yoshihiro Yoneda, Ryuji Yamabi
  • Patent number: 8105902
    Abstract: A semiconductor device with a vertical transistor includes a plurality of active pillars, a plurality of vertical gates surrounding sidewalls of the active pillars; a plurality of word lines having exposed sidewalls whose surfaces are higher than the active pillars and connecting the adjacent vertical gates together, and a plurality of spacers surrounding the exposed sidewalls of the word lines over the vertical gates.
    Type: Grant
    Filed: June 27, 2009
    Date of Patent: January 31, 2012
    Assignee: Hynix Semiconductor Inc.
    Inventor: Jong-Han Shin
  • Patent number: 8106397
    Abstract: A thin film transistor (“TFT”) includes a poly silicon layer formed on a flexible substrate and including a source region, a drain region, and a channel region, and a gate stack formed on the channel region of the poly silicon layer, wherein the gate stack includes first and second gate stacks, and a region of the poly silicon layer between the first and second gate stacks is an off-set region. A method of manufacturing the TFT is also provided.
    Type: Grant
    Filed: June 1, 2007
    Date of Patent: January 31, 2012
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Jang-yeon Kwon, Sang-yoon Lee, Jong-man Kim, Kyung-bae Park, Ji-sim Jung
  • Patent number: 8101473
    Abstract: A process is provided for fabricating rounded three-dimensional germanium active channels for transistors and sensors. For forming sensors, the process comprises providing a crystalline silicon substrate; depositing an oxide mask on the crystalline silicon substrate; patterning the oxide mask with trenches to expose linear regions of the silicon substrate; epitaxially grow germanium selectively in the trenches, seeded from the silicon wafer; optionally etching the SiO2 mask partially, so that the cross section resembles a trapezoid on a stem; and annealing at an elevated temperature. The annealing process forms the rounded channel. For forming transistors, the process further comprises depositing and patterning a gate oxide and gate electrode onto this structure to form the gate stack of a MOSFET device; and after patterning the gate, implanting dopants into the source and drain located on the parts of the germanium cylinder on either side of the gate line.
    Type: Grant
    Filed: July 10, 2009
    Date of Patent: January 24, 2012
    Assignee: Hewlett-Packard Development Company, L.P.
    Inventors: Hans Cho, Theodore I Kamins, Nathaniel Quitoriano
  • Patent number: 8101498
    Abstract: An intermediate substrate includes a handle substrate bonded to a thin layer suitable for epitaxial growth of a compound semiconductor layer, such as a III-nitride semiconductor layer. The handle substrate may be a metal or metal alloy substrate, such as a molybdenum or molybdenum alloy substrate, while the thin layer may be a sapphire layer. A method of making the intermediate substrate includes forming a weak interface in the source substrate, bonding the source substrate to the handle substrate, and exfoliating the thin layer from the source substrate such that the thin layer remains bonded to the handle substrate.
    Type: Grant
    Filed: April 21, 2006
    Date of Patent: January 24, 2012
    Inventors: Thomas Henry Pinnington, James M. Zahler, Young-Bae Park, Charles Tsai, Corinne Ladous, Harry A. Atwater, Jr., Sean Olson
  • Patent number: 8097943
    Abstract: A semiconductor die has active circuits formed on its active surface. Contact pads are formed on the active surface of the semiconductor die and coupled to the active circuits. A die extension region is formed around a periphery of the semiconductor die. Conductive through hole vias (THV) are formed in the die extension region. A wafer level conductive plane or ring is formed on a center area of the active surface. The conductive plane or ring is connected to a first contact pad to provide a first power supply potential to the active circuits, and is electrically connected to a first conductive THV. A conductive ring is formed partially around a perimeter of the conductive plane or ring and connected to a second contact pad for providing a second power supply potential to the active circuits. The conductive ring is electrically connected to a second THV.
    Type: Grant
    Filed: October 15, 2010
    Date of Patent: January 17, 2012
    Assignee: STATS ChipPAC, Ltd.
    Inventors: Guruprasad G. Badakere, Zigmund R. Camacho, Lionel Chien Hui Tay
  • Patent number: 8093694
    Abstract: A non-leaded integrated circuits package system is provided including etching differential height lead structures having inner leads at a paddle height, providing mold locks at the bending points of the differential height lead structures, etching an elevated paddle at a same height as the inner leads, mounting a first integrated circuit on the elevated paddle, and electrically connecting first electrical interconnects between the first integrated circuit and the inner leads.
    Type: Grant
    Filed: November 10, 2005
    Date of Patent: January 10, 2012
    Assignee: Stats Chippac Ltd.
    Inventor: You Yang Ong
  • Patent number: 8093647
    Abstract: A memory cell has a floating gate electrode, a first inter-gate insulating film arranged on the floating gate electrode, and a control gate electrode arranged on the first inter-gate insulating film. An FET has a lower gate electrode, a second inter-gate insulating film having an opening and arranged on the lower gate electrode, a block film having a function to block diffusion of metal atoms and formed on at least the opening, and an upper gate electrode connected electrically to the lower gate electrode via the block film and arranged on the second inter-gate insulating film. The control gate electrode and the upper gate electrode have a Full-silicide structure.
    Type: Grant
    Filed: December 19, 2007
    Date of Patent: January 10, 2012
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Atsuhiro Sato, Mutsumi Okajima
  • Patent number: 8089126
    Abstract: Methods and structures for improving substrate loss and linearity in SOI substrates. The methods include forming damaged crystal structure regions under the buried oxide layer of SOI substrates and the structures included damaged crystal structure regions under the buried oxide layer of the SOI substrate.
    Type: Grant
    Filed: July 22, 2009
    Date of Patent: January 3, 2012
    Assignee: International Business Machines Corporation
    Inventors: Alan Bernard Botula, David S. Collins, Alvin Jose Joseph, Howard Smith Landis, James Albert Slinkman, Anthony K. Stamper
  • Patent number: 8090117
    Abstract: A digital microphone array is configured in an open geometry such as a sphere with a large number of inexpensive microphone elements mounted in opposite-facing pairs. The microphone array with DSP is intended to be placed in a three-dimensional sound field, such as a concert hall or film location, and to completely isolate all sound sources from each other while maintaining their placement in a coherent sound field including reverberance.
    Type: Grant
    Filed: November 21, 2005
    Date of Patent: January 3, 2012
    Inventor: James Cox
  • Patent number: 8086005
    Abstract: A medical image processing apparatus of the present invention includes an edge extracting section that extracts edges of an inputted two-dimensional image, a three-dimensional-model estimating section that estimates a three-dimensional model on the basis of the two-dimensional image, a voxel extracting section that extracts, on the basis of positions of respective voxels, where the edges are present, a predetermined voxel group to be set as a calculation object of a shape feature value, a shape-feature-value calculating section that calculates the shape feature value for at least a part of voxels among the predetermined voxel group, a three-dimensional-shape extracting section that extracts a voxel group, a three-dimensional model of which is estimated as a predetermined shape, on the basis of the shape feature value, and a tuberal-shape detecting section that detects the voxel group as a voxel group forming a tuberal shape in the three-dimensional model of the living tissue.
    Type: Grant
    Filed: September 4, 2008
    Date of Patent: December 27, 2011
    Assignee: Olympus Medical Systems Corp.
    Inventors: Ryoko Inoue, Hirokazu Nishimura, Hideki Tanaka, Kenji Nakamura, Miho Sawa
  • Patent number: 8084305
    Abstract: A semiconductor device comprises a semiconductor mesa overlying a dielectric layer, a gate stack formed overlying the semiconductor mesa, and an isolation spacer formed surrounding the semiconductor mesa and filling any undercut region at edges of the semiconductor mesa.
    Type: Grant
    Filed: February 25, 2008
    Date of Patent: December 27, 2011
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chih-Hsin Ko, Wen-Chin Lee, Yee-Chia Yeo, Chung-Hu Ke
  • Patent number: 8062912
    Abstract: A method of making a semiconductor chip assembly includes providing a post and a base, mounting an adhesive on the base including inserting the post through an opening in the adhesive, mounting a substrate on the adhesive including inserting the post into an aperture in the substrate to form a gap in the aperture between the post and the substrate, then flowing the adhesive into and upward in the gap, solidifying the adhesive, then mounting a semiconductor device on a heat spreader that includes the post and the base, electrically connecting the semiconductor device to the substrate and thermally connecting the semiconductor device to the heat spreader. The substrate includes first and second conductive layers and a dielectric layer therebetween and provides horizontal signal routing between a pad and a terminal at the first conductive layer.
    Type: Grant
    Filed: September 13, 2009
    Date of Patent: November 22, 2011
    Assignee: Bridge Semiconductor Corporation
    Inventors: Chia-Chung Wang, Charles W. C. Lin
  • Patent number: 8063417
    Abstract: In an integrated circuit device, element power supply lines connected to a circuit containing a plurality of cells, element ground lines connected thereto, a trunk power supply line connected to each of the element power supply lines, and a trunk ground line connected to each of the element ground lines are provided in a first wiring layer. A branch power supply line connected to the trunk power supply line and a branch ground line connected to the trunk ground line are provided in an upper wiring layer located above the first wiring layer.
    Type: Grant
    Filed: May 3, 2010
    Date of Patent: November 22, 2011
    Assignee: Panasonic Corporation
    Inventor: Keiichi Kusumoto
  • Patent number: 8058715
    Abstract: In accordance with the present invention, there is provided multiple embodiments of a package-in-package semiconductor device including an RF package and a semiconductor die which are provided in a stacked arrangement and are each electrically connected to an underlying substrate through the use of conductive wires alone or in combination with conductive bumps. In certain embodiments of the present invention, the RF package and the semiconductor die are separated from each other by an intervening spacer which is fabricated from aluminum, or from silicon coated with aluminum. If included in the semiconductor device, the spacer is also electrically connected to the substrate, preferably through the use of conductive wires. The RF package, the semiconductor die, the spacer (if included) and a portion of the substrate are at least partially covered or encapsulated by a package body of the semiconductor device.
    Type: Grant
    Filed: January 9, 2009
    Date of Patent: November 15, 2011
    Assignee: Amkor Technology, Inc.
    Inventors: Fernando Roa, Roger D. St. Amand