Abstract: A semiconductor device, includes: a first storage node contact plug penetrating a first interlayer insulation layer and partially protruding above the first interlayer insulation layer; a second storage node contact plug contacting the first storage node contact plug that protrudes above the first interlayer insulation layer; a storage node contacting a top surface of the second storage node contact plug; and a second interlayer insulation layer formed over the first interlayer insulation layer, wherein the second interlayer insulation layer surrounds an outer sidewall at a bottom region of the first storage node, and the second storage node contact plug, and wherein the first storage node contact plug protruding above the first interlayer insulation layer and the second storage node contact plug.

Abstract: Package (1) having a sensor assembly (2) with at least one sensitive surface (21) and an attachment surface (22), a carrier element (3) with a sensor attachment area (31), and a sensor attach material (4) for attaching the sensor assembly (2) to the sensor attachment area (31) of the carrier element. The package (1) comprises an encapsulation (5) of a first material, in which the encapsulation (5) covers the sensor attachment area (31) of the carrier element (3) and the sensor attach material (4) and leaves the at least one sensitive surface (21) free from the first material.

Abstract: A flexible semiconductor package apparatus having a responsive bendable conductive wire member is presented. The apparatus includes a flexible substrate, semiconductor chips, and conductive wires. The semiconductor chips are disposed on the flexible substrate and spaced apart from each other on the flexible substrate. Each semiconductor chip has bonding pads. The conductive wires are electrically connected to the bonding pads of the semiconductor chip. Each conductive wire has at least one elastic portion. One preferred configuration is that part of the conductive wire is wound to form a coil spring shape so that the coil spring shape of the conductive wire aid in preventing the conductive wire from being separated from the corresponding bonding pad of the semiconductor chip when the flexible substrate on which the semiconductor chips are mounted are bent, expanded or twisted.

Abstract: Herein disclosed a sound inputting and outputting apparatus for being connected to an external apparatus which includes a noise cancel signal production section, a storage section and a reproduction section, including: a first auricle mounting section; a second auricle mounting section; and a plug.

Abstract: A semiconductor device and method for producing such a device is disclosed. One embodiment provides a semiconductor functional wafer having a first and second main surface. Component production processes are performed for producing a component functional region at the first main surface, wherein the component production processes produce an end state that is stable up to at least a first temperature. A carrier substrate is fitted to the first main surface. Access openings are produced to the first main surface. At least one further component production process is performed for producing patterned component functional regions at the first main surface of the functional wafer in the access openings. The end state produced in this process is stable up to a second temperature, which is less than the first temperature.

Abstract: A semiconductor structure. The semiconductor structure includes a semiconductor layer, a charge accumulation layer on top of the semiconductor layer, a doped region in direct physical contact with the semiconductor layer; and a device layer on and in direct physical contact with the charge accumulation layer. The charge accumulation layer includes trapped charges of a first sign. The doped region and the semiconductor layer forms a P?N junction diode. The P?N junction diode includes free charges of a second sign opposite to the first sign. The trapped charge in the charge accumulation layer exceeds a preset limit above which semiconductor structure is configured to malfunction. A first voltage is applied to the doped region. A second voltage is applied to the semiconductor layer. A third voltage is applied to the device layer. The third voltage exceeds the first voltage and the second voltage.

Abstract: Embodiments provide an electronic device including a leadframe, a chip attached to the leadframe, and encapsulation material disposed over a portion of the leadframe. The leadframe includes a first main face opposite a second main face and a plurality of edges extending between the first and second main faces. At least one of the plurality of edges includes a first profiled element and a second profiled element different than the first profiled element. The encapsulation material is disposed over the chip and the plurality of edges of the leadframe.

Abstract: An EEPROM according to the present invention includes: a semiconductor layer of a first conductive type; and a first insulating film formed on the semiconductor layer. A first impurity region, a second impurity region, a third impurity region, a fourth impurity region, and a fifth impurity region of a second conductive type are formed in top layer portions of the semiconductor layer. On the first insulating film, a select gate, a first floating gate, and a second floating gate are respectively disposed opposite a region between the first impurity region and the second impurity region, a region between the second impurity region and the third impurity region, and a region between the third impurity region and the fourth impurity region. In the first insulating film, a first tunnel window and a second tunnel window are respectively formed at portions in contact with the first floating gate and the second floating gate.

Abstract: Data retention in flash memory devices, such as mirrorbit devices, is improved by reducing the generation and/or diffusion of hydrogen ions during back end processing, such as annealing inlaid Cu. Embodiments include annealing inlaid Cu in an N2 atmosphere containing low H2 or no H2, and at temperatures less than 200° C., e.g., 100° C. to 150° C.

Abstract: A trenched semiconductor power device includes a trenched gate insulated by a gate insulation layer and surrounded by a source region encompassed in a body region above a drain region disposed on a bottom surface of a semiconductor substrate. The source region surrounding the trenched gate includes a metal of low barrier height to function as a Schottky source. The metal of low barrier height further may include a PtSi or ErSi layer. In a preferred embodiment, the metal of low barrier height further includes an ErSi layer. The metal of low barrier height further may be a metal silicide layer having the low barrier height. A top oxide layer is disposed under a silicon nitride spacer on top of the trenched gate for insulating the trenched gate from the source region. A source contact disposed in a trench opened into the body region for contacting a body-contact dopant region and covering with a conductive metal layer such as a Ti/TiN layer.

Abstract: A method of making a semiconductor chip assembly includes providing a post and a base, mounting an adhesive on the base including inserting the post through an opening in the adhesive, mounting a substrate on the adhesive including inserting the post into an aperture in the substrate to form a gap in the aperture between the post and the substrate, then flowing the adhesive into and upward in the gap, solidifying the adhesive, then mounting a semiconductor device on a heat spreader that includes the post and the base, electrically connecting the semiconductor device to the substrate and thermally connecting the semiconductor device to the heat spreader. The substrate includes first and second conductive layers and a dielectric layer therebetween, and the assembly provides the vertical signal routing between a pad at the first conductive layer and a terminal below the adhesive.

Abstract: An array substrate includes first and second gate electrodes on a substrate; a gate insulating layer on the first and second gate electrodes; first and second active layers on the gate insulating layer; an interlayer insulating layer on the first and second active layers; first to fourth ohmic contact layers respectively contacting both sides of the first active layer and both sides of the second active layer; first and second source electrodes and first and second drain electrodes respectively on the first, third, second and fourth ohmic contact layers; a data line connected to the first source electrode; a first passivation layer connected to the first gate electrode; a power line; one end and the other end of a connection electrode respectively connected to the first drain electrode and the second gate electrode; a second passivation layer; and a pixel electrode-connected to the second drain electrode.

Abstract: The present invention provides a method for forming a silica-containing film with a low-dielectric constant of 3 or less on a semiconductor substrate steadily, which comprises steps of (a) applying a coating liquid for forming the silica-containing film with the low-dielectric constant onto the semiconductor substrate, (b) heating the thus coated film at 50 to 350° C., and then (c) curing the thus treated film at 350 to 450° C. in an inert-gas atmosphere containing 500 to 15,000 ppm by volume of oxygen, and also provides a semiconductor substrate having a silica-containing film formed by the above method. The above step (b) for the thermal treatment is preferably conducted at 150 to 350° C. for 1 to 3 minutes in an air atmosphere. Also, the above curing step (c) is preferably conducted by placing the semiconductor substrate on a hot plate kept at 350 to 450° C.