Abstract: To provide a highly integrated semiconductor memory device. To provide a semiconductor memory device which can hold stored data even when power is not supplied. To provide a semiconductor memory device which has a large number of write cycles. The degree of integration of a memory cell array is increased by forming a memory cell including two transistors and one capacitor which are arranged three-dimensionally. The electric charge accumulated in the capacitor is prevented from being leaking by forming a transistor for controlling the amount of electric charge of the capacitor in the memory cell using a wide-gap semiconductor having a wider band gap than silicon. Accordingly, a semiconductor memory device which can hold stored data even when power is not supplied can be provided.

Abstract: A technique for forming an integrated circuit including an inductor reduces magnetic coupling between the inductor and surrounding elements. The technique includes deliberate placement of circuit elements (e.g., terminals, pins, routing traces) in locations on the integrated circuit relative to a magnetic vector potential associated with the inductor and relative to a magnetic flux density field associated with the inductor to reduce or eliminate induced signals that degrade system performance.

Abstract: A micro-printed display includes a display substrate. An array of row conductors, an array of column conductors, and a plurality of micro-pixels are disposed on the display substrate. Each micro-pixel is uniquely connected to a row and a column conductor and comprises a pixel substrate separate from the display substrate and the pixel substrate of any other micro-pixel. Pixel conductors are patterned on each pixel substrate and one or more LEDs are disposed on or over the pixel substrate. Each LED is electrically connected to one or more of the pixel conductors and has an LED substrate separate from any other LED substrate, the display substrate, and any pixel substrate. A pixel controller disposed on the pixel substrate can control the LEDs. The micro-pixel can be electrically connected to the display substrate with connection posts. Redundant or replacement LEDs or micro-pixels can be provided on the pixel or display substrate.

Abstract: A micro-transfer printable electronic component includes one or more electronic components, such as integrated circuits or LEDs. Each electronic component has device electrical contacts for providing electrical power to the electronic component and a post side. A plurality of electrical conductors includes at least one electrical conductor electrically connected to each of the device electrical contacts. One or more electrically conductive connection posts protrude beyond the post side. Each connection post is electrically connected to at least one of the electrical conductors. Additional connection posts can form electrical jumpers that electrically connect electrical conductors on a destination substrate to which the printable electronic component is micro-transfer printed. The printable electronic component can be a full-color pixel in a display.

Abstract: A method can be used to make a semiconductor device. A number of projecting regions are formed over a first semiconductor layer that has a first conductivity type. The first semiconductor layer is located on an insulating layer that overlies a semiconductor substrate. The projecting regions are spaced apart from each other. Using the projecting regions as an implantation mask, dopants having a second conductivity type are implanted into the first semiconductor layer, so as to form a sequence of PN junctions forming diodes in the first semiconductor layer. The diodes vertically extend from an upper surface of the first semiconductor layer to the insulating layer.

Abstract: A transistor includes a substrate having an upper surface, a fin structure protruding from the upper surface of the substrate, a first isolation structure over the upper surface of the substrate, and a second isolation structure. The fin structure extends along a first direction and comprising a lower portion and an upper portion. The first isolation structure surrounds the lower portion of the fin structure. The second isolation structure is at least partially embedded in the upper portion of the fin structure.

Abstract: A semiconductor device includes a semiconductor substrate of silicon carbide, and a temperature sensor portion. The semiconductor substrate includes a portion in which an n-type drift region and a p-type body region are laminated. The temperature sensor portion is disposed in the semiconductor substrate and is separated from the drift region by the body region. The temperature sensor portion includes an n-type cathode region being in contact with the body region, and a p-type anode region separated from the body region by the cathode region.

Abstract: In a semiconductor device including a gate line having a relatively narrow width and a relatively smaller pitch and a method of manufacturing the semiconductor device, the semiconductor device includes a substrate having a fin-type active region, a gate insulating layer that covers an upper surface and sides of the fin-type active region, and a gate line that extends and intersects the fin-type active region while covering the upper surface and the both sides of the fin-type active region, the gate line being on the gate insulating layer, wherein a central portion of an upper surface of the gate line in a cross-section perpendicular to an extending direction of the gate line has a concave shape.

Abstract: A substrate treating apparatus including an unloading order changing unit. The unloading order changing unit reverses an order, in regard to unloading of substrates in a carrier from the top, between a poor inclined substrate and a substrate at least immediately above the poor inclined substrate when the poor inclined substrate is present whose inclination is determined larger than a pre-set threshold by a poor inclination determining unit. That is, the order is reversed such that the poor inclined substrate whose surface may be possibly be scratched with a hand is unloaded prior to the substrate immediately above the poor inclined substrate. Accordingly, this inhibits damages on the substrate caused by scratching a substrate surface with the hand of a substrate transport mechanism.

Abstract: A method for fabricating a semiconductor component includes forming an interlayer dielectric (ILD) layer on a substrate, forming a trench in the interlayer dielectric layer, forming a metal gate in the trench, removing a portion of the metal gate protruding from the ILD layer, reacting a reducing gas with the metal gate, and removing a top portion of the metal gate.

Abstract: An integrated circuit structure includes a package component, which further includes a non-porous dielectric layer having a first porosity, and a porous dielectric layer over and contacting the non-porous dielectric layer, wherein the porous dielectric layer has a second porosity higher than the first porosity. A bond pad penetrates through the non-porous dielectric layer and the porous dielectric layer. A dielectric barrier layer is overlying, and in contact with, the porous dielectric layer. The bond pad is exposed through the dielectric barrier layer. The dielectric barrier layer has a planar top surface. The bond pad has a planar top surface higher than a bottom surface of the dielectric barrier layer.

Abstract: An exemplary embodiment of the present disclosure provides a display device including: a substrate including a display area and a non-display area; a COF package overlapped with the non-display area of the substrate; a printed circuit board (PCB) overlapped with the COF package; a plurality of pixels disposed on the display area of the substrate; a plurality of data lines connected to the plurality of pixels; a first crack sensing line disposed on the non-display area of the substrate; a second crack sensing line that extends to be parallel to the first crack sensing line on the non-display area of the substrate and is connected to the first data line of the plurality of data lines; a first dummy wire that is disposed on the COF package and is overlapped with the first crack sensing line and the second crack sensing line; a first anisotropic conductive film disposed between the substrate and the COF package; a first test pattern and a second test pattern disposed on the PCB; a third test pattern that is dispo

Abstract: Some embodiments include a memory cell having first, second and third transistors, with the second and third transistors being vertically displaced relative to one another. The memory cell has a semiconductor pillar extending along the second and third transistors, with the semiconductor pillar containing channel regions and source/drain regions of the second and third transistors. A capacitor may be electrically coupled between a source/drain region of the first transistor and a gate of the second transistor.

Abstract: A method for manufacturing a semiconductor device may include forming a semiconductor portion, forming a doped portion, and forming a dielectric member. A side of the dielectric member abuts each of the semiconductor portion and the doped portion. A first half of the doped portion is positioned between the semiconductor portion and a second half of the doped portion. A dopant concentration of the second half of the doped portion is greater than a dopant concentration of the first half of the doped portion.

Abstract: A manufacturing method of a semiconductor storage device includes forming a plurality of bit line structures on a semiconductor substrate and forming a plurality of storage node contacts disposed between the bit line structures. The method of forming the storage node contacts includes forming a plurality of conductive patterns on the semiconductor substrate followed by performing an etching back process to the conductive patterns for decreasing a thickness of the conductive patterns. The manufacturing method further includes forming a plurality of isolation patterns between the conductive patterns, wherein the isolation patterns are formed after forming the plurality of conductive patterns and before the etching back process. According to the present invention, the storage node contacts are formed by first forming the conductive patterns and then forming the isolation patterns between the conductive patterns, so as to simplify manufacturing process and increase process yield.

Abstract: A semiconductor device includes an oxide semiconductor layer, a source electrode and a drain electrode electrically connected to the oxide semiconductor layer, a gate insulating layer covering the oxide semiconductor layer, the source electrode, and the drain electrode, and a gate electrode over the gate insulating layer. The source electrode and the drain electrode include an oxide region formed by oxidizing a side surface thereof. Note that the oxide region of the source electrode and the drain electrode is preferably formed by plasma treatment with a high frequency power of 300 MHz to 300 GHz and a mixed gas of oxygen and argon.

Abstract: Some embodiments include a memory cell having a first transistor supported by a semiconductor base, and having second and third transistors above the first transistor and vertically stacked one atop the other. Some embodiments include a memory cell having first, second and third transistors. The third transistor is above the second transistor, and the second and third transistors are above the first transistor. The first transistor has first and second source/drain regions, the second transistor has third and fourth source/drain regions, and the third transistor has fifth and sixth source/drain regions. A read bitline is coupled with the sixth source/drain region. A write bitline is coupled with the first source/drain region. A write wordline includes a gate of the first transistor. A read wordline includes a gate of the third transistor. A capacitor is coupled with the second source/drain region and with a gate of the second transistor.

Abstract: According to one embodiment, a semiconductor device includes a semiconductor substrate, a stacked body, and a first insulating film. The stacked body is provided on the semiconductor substrate. The stacked body includes first films, and second films being conductive. The first films and the second films are stacked alternately. The first insulating film extends in a stacking direction of the stacked body. The second films include a first portion and a second portion. The first portion is positioned between the first films. The second portion has a surface contacting the first insulating film in a direction perpendicular to the stacking direction.

Abstract: A package includes first package component, which further includes a first metal trace at a surface of the first package component, with the first metal trace having a trace width measured in a direction perpendicular to a lengthwise direction of the first metal trace. The first package component further includes a second metal trace at the surface of the first package component. The first metal trace and the second metal trace are parallel to each other. A second package component is overlying the first package component, wherein the second package component includes a metal bump. A solder region bonds the metal bump to the first metal trace, wherein the solder region contacts a top surface and sidewalls of the first portion of the first metal trace. A ratio of a volume of the solder region to the trace width is between about 1,100 ?m2 and about 1,300 ?m2.

Abstract: A method includes forming a dummy gate stack over a semiconductor region, forming a dielectric layer at a same level as the dummy gate stack, removing the dummy gate stack to form an opening in the dielectric layer, filling a metal layer extending into the opening, and etching back the metal layer, with remaining portions of the metal layer having edges lower than a top surface of the dielectric layer. The opening is filled with a conductive material, and the conductive material is over the metal layer. The metal layer and the conductive material in combination form a replacement gate. A source region and a drain region are formed on opposite sides of the replacement gate.