Abstract: A method for storing information in SRAM bit cell arrays provides for lowering voltage supplied to the SRAM bit cell arrays, with voltage lowering controlled by a connected voltage control circuit. Writing, reading, and correcting information storable in the SRAM bit cell arrays is accomplished using an error correcting code (ECC) block connected to at least some of the SRAM bit cell arrays. The ECC block is configurable to repair stored information.

Abstract: A memory system includes a memory track including a plurality of magnetic domains having alternating magnetic polarities and positioned along a path, and a plurality of domain walls separating adjacent ones of the plurality of magnetic domains, each one of the domain walls being configured to store data.

Abstract: A method is presented for mitigating conductance drift in intercalation cells for neuromorphic computing. The method includes forming a first electro-chemical random access memory (ECRAM) structure over a substrate and forming a second ECRAM over the substrate, the first and second ECRAMs sharing a common contact. The common contact can be either a source contact or a drain contact. Each of the first and second ECRAMs can include a tungsten oxide layer, an electrolyte layer, and a gate contact.

Abstract: A method for initializing a channel in a non-volatile memory device comprising a memory block including a plurality of word lines and a plurality of string selection lines, includes applying a voltage to the plurality of string selection lines; converting a bit line passing through the block into a floating state; and a releasing the floating state of the bit line.

Abstract: Memory devices for embedded applications are described. A memory device may include an array of memory cells having a first area and configured to operate at a first voltage, and circuitry having a second area that at least partially overlaps the first area. The circuitry may be configured to operate at a second voltage lower than the first voltage. The circuitry maybe be further configured to access the array of memory cells using decoder circuitry configured to operate at the first voltage. The array of memory cells and the circuitry may be on a single substrate. The circuitry may include microcontroller circuitry, cryptographic controller circuitry, and/or memory controller circuitry. The memory cells may be self-selecting memory cells that each include a storage and selector element having a chalcogenide material. The memory cells may not include separate cell selector circuitry.

Abstract: The claimed subject matter relate to circuits and/or methods, which operate to introduce a variable delay in a write-assist signal to a write driver of an array of SRAM cells. Particularly, a variable delay may be introduced by way of a voltage tracking circuit, which may generate a trigger signal in response to a voltage signal from an array of access devices that replicate access devices of the array of SRAM cells.

Abstract: A semiconductor memory cell including a capacitorless transistor having a floating body configured to store data as charge therein when power is applied to the cell, and a non-volatile memory comprising a bipolar resistive change element, and methods of operating.

Abstract: A semiconductor storage device includes first high-potential wirings, second high-potential wirings, a first low-potential wiring, a second low-potential wiring, a first branch wiring, and a second branch wiring formed in a wiring layer between a memory cell array and a semiconductor substrate and each extending in a first direction. The first branch wiring is electrically connected to the first low-potential wiring, and is adjacent to the first low-potential wiring on one side in a second direction perpendicular to the first direction of the first low-potential wiring. The second branch wiring is electrically connected to the second low-potential wiring, and is adjacent to the second low-potential wiring on the other side in the second direction of the second low-potential wiring. A first via is provided to contact the first branch wiring, and a second via is provided to contact the second branch wiring.

Abstract: Systems and methods of use and fabrication are described for a non-volatile resistive random access memory (RRAM) multi-terminal device including a first electrode, a second electrode, a metal oxide disposed between the first electrode and the second electrode, and an at least first gate configured to apply a voltage bias to change a resistive state in the metal oxide.

Abstract: A memory device includes a plurality of memory cells arranged in an array having a plurality of rows and a plurality of columns. A first word line is connected to a first plurality of the memory cells of a first row of the array, and a second word line is connected to a second plurality of the memory cells of the first row of the array. In some examples, the plurality of memory cells are arranged in or on a substrate, and the first word line is formed in a first layer of the substrate and the second word line is formed in a second layer of the substrate.

Abstract: An analog content addressable memory cell includes a high side and a low side. The high side encodes a high bound on a range of values and includes a first voltage divider formed of a first programmable resistor and a first electronically controlled variable resistor. The low side encodes a low bound on the range of values and includes a second voltage divider formed of a second programmable resistor and a second electronically controlled variable resistor.

Abstract: A method of operating a memory controller performing activation of a memory device, the method including determining a selection signal for each tile column in a memory block of the memory device by activating respective local word lines, wherein the block selection signal is determined by performing a radix n operation on a vector identifying elements to be read or written.

Abstract: A receiver implemented in an integrated circuit device is described. The receiver circuit comprises a first receiver circuit configured to receive first data, wherein the first receiver circuit comprises a first memory element configured to receive the first data in response to a first clock signal; a latency mirror circuit configured to receive second data, wherein the latency mirror circuit comprises a second memory element configured to receive the second data in response to a second clock signal; and a latency control circuit configured to detect a latency in the second data, wherein the latency control circuit adjusts a phase of the first clock signal used to receive the first data in the first receiver circuit.

Abstract: A semiconductor device includes a memory cell array, a plurality of word lines, a plurality of bit line pairs, a column selection circuit coupling a bit line pair in a selected column in the plurality of bit line pairs to first and second output signal lines on the basis of a column selection signal, and a sense amplifier amplifying the voltage difference between the first and second output signal lines. The semiconductor device further includes: a scan flip flop to which the data can be input via a scan chain; and a voltage setting circuit setting the first and second output signal lines to voltage according to the data held in the scan flip flop in a scan test.

Abstract: Methods, systems, and devices for spare substitution in a memory system are described. memory device identifying a rotation index that indicates a first assignment of logical channel to physical channels for code words stored in a memory medium. The memory device may use a pointer to indicate one or more code word addresses that are to be rotated and update a value of the pointer associated with a range for the rotation index based on a condition being satisfied. The memory device may rotate a first code word according to a first assignment of the rotation index, where the rotating may occur at an address of the memory medium corresponding to the updated value of the pointer. Additionally, the memory device may execute access operations on the memory medium that include multiplexing multiple logical channels to multiple physical channels based on the rotation index and the pointer.

Abstract: A logic integrated circuit includes: a three-terminal resistance change switch including a first resistance change switch and a second resistance change switch connected in series; a reading circuit which reads first data based on a resistance state of the first resistance change switch and second data based on a resistance state of the second resistance change switch; and a first error detection circuit which compares the first data with the second data and issue an output based on a result of the comparison.

Abstract: Memory devices and systems with on-die data transfer capability, and associated methods, are disclosed herein. In one embodiment, a memory device includes an array of memory cells and a plurality of input/output lines operably connecting the array to data pads of the device. In some embodiments, the memory device can further include a global cache and/or a local cache. The memory device can be configured to internally transfer data stored at a first location in the array to a second location in the array without outputting the data from the memory device. To transfer the data, the memory device can copy data on one row of memory cells to another row of memory cells, directly write data to the second location from the first location using data read/write lines of the input/output lines, and/or read the data into and out of the global cache and/or the local cache.

Abstract: A static random access memory cell includes first and second cross-coupled inverters, a write transistor and a read transistor. The first inverter has a first latch node and the second inverter has a second latch node. The write transistor is coupled in series with a wordline transistor between the first latch node of the first inverter and a bitline. The read transistor is coupled between the bitline and a reference terminal and has a control terminal coupled to the first latch node of the first inverter. A method of operating the static random access memory cell includes enabling the wordline transistor during a write operation, and enabling the write transistor during the write operation. The reference terminal is set to floating during the write operation.

Abstract: A preheating procedure for a non-volatile memory that can be used in a wide range of ambient temperatures is shown. The controller of the non-volatile memory operates the non-volatile memory to preheat the non-volatile to a temperature target. The controller avoids writing valid data to the non-volatile memory until preheating the non-volatile memory to the temperature target. The controller may write or read dummy data to or from the non-volatile memory until preheating the non-volatile memory to the temperature target.

Abstract: An input/output multiplexer is provided and coupled to a memory array through bit lines. The input/output multiplexer includes a bit-line amplifier, a level-raising circuit, and a sensing amplifier. The bit-line amplifier amplifies a voltage difference between voltage levels of first and second bit lines in a read mode. In a first selection period of the read mode, according to the amplified voltage difference, a voltage level of a first local-data terminal of the bit-line amplifier is initially at an initial level, and a voltage level of a second local-data terminal thereof decreases from the initial level toward that of a low supply voltage. The level-raising circuit raises the voltage level of the first local-data terminal from the initial level in the first selection period. The sensing amplifier generates readout data according to the raised voltage level of the first local-data terminal and the voltage level of the second local-data terminal.