Abstract: A bit cell is described. In some embodiments, the bit cell comprises (1) a magnetic tunnel junction (MTJ), and (2) an access transistor circuit coupled to the MTJ, wherein the access transistor circuit comprises a negative-capacitance field-effect-transistor.

Abstract: An embodiment includes an apparatus comprising: a thin film transistor (TFT) comprising: source and drain contacts; first and second gate contacts: a semiconductor material, comprising a channel, between the first and second gate contacts; and a first dielectric layer, between the first and second gate contacts, to fix charged particles. Other embodiments are described herein.

Abstract: RRAM devices with tunable forming voltage are provided herein. A method of forming an RRAM device includes: depositing a first dielectric layer on a substrate; forming metal pads in the first dielectric layer; depositing a capping layer onto the first dielectric layer; forming heating elements in the capping layer in contact with the metal pads; forming an RRAM stack on the capping layer; patterning the RRAM stack into an RRAM cell(s) including a bottom electrode, a high-? switching layer disposed on the bottom electrode, and a top electrode disposed on the high-? switching layer; depositing a second dielectric layer over the RRAM cell(s); and forming a contact to the top electrode in the second dielectric layer. An RRAM device and a method of operating an RRAM device are also provided.

Abstract: Provided is a manufacturing process for electronic circuit components such as bare dies, and packaged integrated chips, among other configurations, to form electronic assemblies. The surface of the electronic circuit component carries electronic elements such as conductive traces and/or other configurations including contact pads. A method for forming an electronic assembly includes providing a tacky layer. Then an electronic circuit component is provided having a first side and a second side, where the first side carries the electronic elements. The first side of the electronic circuit component is positioned into contact with the tacky layer. A bonding material is then deposited to a portion of the adhesive layer that is not covered by the first side of the electronic circuit component, to a depth which is sufficient to cover at least a portion of the electronic circuit component. The bonding material is then fixed or cured into a fixed or cured bonding material, and the tacky layer is removed.

Abstract: An erasable magnetoresistive random-access memory (MRAM) structure and a method of making the same includes an MRAM cell disposed between bit line and word line circuit elements, and a vertical-cavity surface-emitting laser (VCSEL) element disposed above the MRAM cell. A laser output of the VCSEL is directed toward the MRAM cell.

Abstract: Systems and methods for reducing column switch resistance error RRAM-based crossbar array circuits are disclosed. An example crossbar array circuit includes: a crossbar array including a row wire, a column wire, and a cross-point device connected between the row wire and the column wire; a column switch having a column switch input and a column switch output, connected to the cross-point device; an Op-amp device having a non-inverting input, an inverting input, and an Op-amp output; a three-terminal switch having a first terminal, a second terminal, and a third terminal. The three-terminal switch is connected to the inverting input and is configured to switch between the column switch input and the column switch output; a load resistor is connected with the column switch output and the Op-amp output.

Abstract: A search circuit includes a content-addressable memory (CAM) including a plurality of CAM cells configured to store a plurality of entry data, each entry data including a first bit corresponding to a least significant bit through a K-th bit corresponding to a most significant bit, the CAM configured to provide a plurality of matching signals indicating whether each of the plurality of entry data matches searching data, and a CAM controller configured to perform a partial searching operation such that the CAM controller applies comparison bits corresponding to a portion of the first through K-th bits as the searching data to the CAM and searches for target entry data among the plurality of entry data based on the plurality of matching signals indicating that the corresponding bits of the target entry data match the comparison bits.

Abstract: A data transfer circuit and a memory device including the data transfer circuit are provided. The data transfer circuit includes a first regulator provided with an external voltage to output a first internal voltage; a second regulator configured in a same manner as the first regulator and provided with the external voltage to output a second internal voltage; an amplifier configured for amplifying noise between the first internal voltage and the second internal voltage to output an amplification voltage; and a plurality of peripheral circuits performing by being provided with the first internal voltage.

Abstract: A memory device and a reading method thereof are provided. During a second reading period, a second bit line voltage is provided to a bit line having a read finished memory cell. Thus, a voltage difference between a bit line voltage and a pass voltage of memory cells on unselected word lines is reduced. A data value stored in the memory cells on a selected word line is determined according to whether the memory cells on the selected word line enter a preset state during a first reading period and the second reading period.

Abstract: A semiconductor memory device includes a memory cell array; a page buffer circuit including a plurality of page buffers which are coupled to the memory cell array through a plurality of bit lines which extend in a second direction intersecting with a first direction; and a cache latch circuit including a plurality of cache latches which are coupled to the plurality of page buffers. The plurality of cache latches have a two-dimensional arrangement in the first direction and the second direction. Among the plurality of cache latches, an even cache latch and an odd cache latch which share a data line and an inverted data line are disposed adjacent to each other in the first direction.

Abstract: 3D memory devices with an etch-resistant layer and methods for forming the same are disclosed. A memory device includes a substrate and a memory stack disposed on the substrate. The memory stack includes a plurality of interleaved conductor layers and dielectric layers. The memory device also includes a plurality of memory strings each extending vertically through the memory stack and including a semiconductor plug at a bottom portion of the memory string. The semiconductor plug is in contact with the substrate and includes a top portion doped with an etch-resistant material.

Abstract: A control circuit capable of generating a reliable reference potential while suppressing increase in power consumption and cost. A control circuit causes write processing to be performed individually for a first reference element set to a first resistance state in generating a reference potential used for reading data from a memory element, and a second reference element different from the first reference element, the second reference element being set to a second resistance state different from the first resistance state in generating the reference potential.

Abstract: A flash memory of the invention has a plurality of planes, a controller, a switch unit, and a driving control circuit. The controller is configured to select at least one of the planes. The switch unit is configured to electrically connect bit lines of the unselected plane to a reference voltage. The driving control circuit is configured to commonly provide a gate select signal to select transistors of the selected planes and the unselected planes after the bit lines of the unselected plane is electrically connected to the reference voltage. A flash memory that can reliably seek stability of threshold distribution of memory is provided.

Abstract: Provided are a non-volatile memory device and an erasing method thereof.

Abstract: A multi-gate transistor includes: a doped drain region; a doped source region; a gate group including a first gate and a second gate; a channel, the doped drain region and the doped source region being on respective two sides of the channel; and an interlayer, formed between the channel and the gate group, wherein a first gate voltage and a second gate voltage are applied to the first gate and the second gate of the gate group, respectively, the channel is induced as at least a P sub-channel and at least an N sub-channel and the multi-gate transistor equivalently behaves as a PNPN structure.

Abstract: A 2T-2S SRAM cell exhibiting a complementary scheme, that includes two selector devices that exhibit negative differential resistance. Advantages include lower area and better performance than traditional SRAM cells, according to some embodiments. The term 1T-1S refers to a transistor in series with a selector device. Accordingly, the term 2T-2S refers to two such 1T-1S structures.

Abstract: A memory cell includes a write port and a read port. The write port includes two cross-coupled inverters that form a storage unit. The cross-coupled inverters are connected between a first power source signal line and a second power source signal line. The write port also includes a first local interconnect line in an interconnect layer that is connected to the second power source signal line. The read port includes a transistor that is connected to the storage unit in the write port and to the second power source signal line, and a second local interconnect line in the interconnect layer that is connected to the second power source signal line. The second local interconnect line in the read port is separate from the first local interconnect line in the write port.

Abstract: A system for DNA gene assembly that utilizes a DNA symbol library and a DNA linker library. The symbol library has a number of DNA symbols each having a first overhanging end and a second overhanging end different than and non-complimentary to the first end, the first and second ends being the same nucleotides for each DNA symbol. The linker library has pairs of DNA linkers, a first linker of a pair having a first overhanging end and a second overhanging end and a second linker of the pair having a first overhanging end and a second overhanging end, the first end of the first linker being the same nucleotides for each first linker and the second end of the second linker being the same nucleotides for each second linker, wherein the second end of the first linker and the first end of the second linker have complementary nucleotides. The first linker joins to the first end of a DNA symbol and the second linker joins to the second end of another DNA symbol.

Abstract: A wireless system is provided for monitoring environmental, soil, or climate conditions and/or controlling irrigation or climate control systems at an agricultural or landscape site. In some embodiments, the wireless system includes at least one wireless control nodes for monitoring environmental, soil, or climate conditions and/or for controlling one or more irrigation or climate control systems at the site. The wireless system also includes a web based application or a cell phone application and a gateway coupled to a communications network. The communications network is configured to transfer data to and receive remote control commands or queries from an end-user.

Abstract: Memory with partial bank refresh is disclosed herein. In one embodiment, a memory system includes a memory controller and a memory device operably connected to the memory controller. The memory device includes (i) a memory array having a memory bank with a plurality of memory cells arranged in a plurality of memory rows and (ii) circuitry. In some embodiments, the circuitry is configured to disable at least one memory row of the memory bank from receiving refresh commands such that memory cells of the at least one memory row are not refreshed during refresh operations of the memory device. In some embodiments, the memory controller is configured to track memory rows that include utilized memory cells and/or to write data to the memory rows in accordance with a programming sequence of the memory device.