Abstract: Semiconductor devices and methods of manufacturing the same are disclosed. In some embodiments, a method of manufacturing a semiconductor device comprises forming a fin structure over a substrate. The fin structure may comprise a lower portion protruding from a major surface of the substrate, an upper portion, and a middle portion between the lower portion and the upper portion, wherein the lower portion and the middle portion differ in composition. The method may further include forming an isolation structure surrounding the fin structure and oxidizing the fin structure. The oxidizing may form a pair of notches extending from sidewalls of the fin structure into the middle portion of the fin structure.

Abstract: A method for fabricating an LED/phosphor structure is described where an array of blue light emitting diode (LED) dies are mounted on a submount wafer. A phosphor powder is mixed with an organic polymer binder, such as an acrylate or nitrocellulose. The liquid or paste mixture is then deposited over the LED dies or other substrate as a substantially uniform layer. The organic binder is then removed by being burned away in air, or being subject to an O2 plasma process, or dissolved, leaving a porous layer of phosphor grains sintered together. The porous phosphor layer is impregnated with a sol-gel (e.g., a sol-gel of TEOS or MTMS) or liquid glass (e.g., sodium silicate or potassium silicate), also known as water glass, which saturates the porous structure. The structure is then heated to cure the inorganic glass binder, leaving a robust glass binder that resists yellowing, among other desirable properties.

Abstract: An electrical or electronic device is disclosed. In some embodiments, an electrical device includes a single-layer graphene part extending in a lateral direction and a multi-layer graphene structure laterally contacting the single-layer graphene part. The electrical or electronic device further includes a graphite part in contact with a surface of the multi-layer graphene structure. In other embodiments, an electrical device includes a graphene part extending in a lateral direction and a graphite part is configured to provide a lateral contact for the graphene part.

Abstract: A method for fabricating an LED/phosphor structure is described where an array of blue light emitting diode (LED) dies are mounted on a submount wafer. A phosphor powder is mixed with an organic polymer binder, such as an acrylate or nitrocellulose. The liquid or paste mixture is then deposited over the LED dies or other substrate as a substantially uniform layer. The organic binder is then removed by being burned away in air, or being subject to an O2 plasma process, or dissolved, leaving a porous layer of phosphor grains sintered together. The porous phosphor layer is impregnated with a sol-gel (e.g., a sol-gel of TEOS or MTMS) or liquid glass (e.g., sodium silicate or potassium silicate), also known as water glass, which saturates the porous structure. The structure is then heated to cure the inorganic glass binder, leaving a robust glass binder that resists yellowing, among other desirable properties.

Abstract: In one embodiment a method of etching a substrate includes directing a first ion beam to the substrate through an extraction plate of a processing apparatus using a first set of control settings of the processing apparatus. The method may further include detecting a signal from the substrate that indicates a change in material being etched by the first ion beam from a first material to a second material, adjusting control settings of the processing apparatus to a second set of control settings different from the first set of control settings based on the second material, and directing a second ion beam to the substrate through the extraction plate using the second set of control settings.

Abstract: In one aspect there is set forth herein a semiconductor structure having fins extending upwardly from an ultrathin body (UTB). In one embodiment a multilayer structure can be disposed on a wafer and can be used to pattern voids extending from a UTB layer of the wafer. Selected material can be formed in the voids to define fins extending upward from the UTB layer. In one embodiment silicon (Si) can be grown within the voids to define the fins. In one embodiment, germanium based material can be grown within the voids to define the fins.

Abstract: A blue light emitting device includes an electrode layer, a first metal layer, a second metal layer formed between the electrode layer and the first metal layer, and an organic material layer formed between the first metal layer and the second metal layer and including a blue shift light emitting sub-layer. A peak of a first light-emitting spectrum of the blue shift light emitting sub-layer, which ranges within 490-550 nm, is shifted to a peak of a second light-emitting spectrum, which is less than 510 nm, by the surface plasmon coupling between the first metal layer and the second metal layer. A light emitting device is further provided, which is sequentially stacked with a first metal layer, an organic material layer having a blue shift light emitting sub-layer, a second metal layer having a metal portion and an opening portion, an electrode layer, and a light emitting layer doped with a dopant material, to emit white light.

Abstract: One or more systems and methods for reshaping a hard mask are provided. A semiconductor arrangement comprises one or more structures formed from a layer according to a target dimension, such as a width criterion, a length criterion, a spacing criterion, or other design constraints. To form such a structure, a hard mask is formed over the layer. Responsive to a dimension, such as a width, of the hard mask not corresponding to the target dimension, a first hard mask portion is modified to create a modified hard mask comprising a modified first hard mask portion. In some embodiments, the first hard mask portion is trimmed to decrease the dimension or coated with a coating material to increase the dimension. An etch of the layer is performed through the modified hard mask to create an etched layer comprising an etched portion, such as the structure, corresponding to the target dimension.

Abstract: The present disclosure relates to a MEMS device with a magnetic film disposed on a first substrate, and an associated method of formation. In some embodiments, the magnetic film is disposed on a planar front surface of the first substrate such that depositing and patterning processes of the magnetic film is improved. A sensing gap of a MEMS device associated with the magnetic film is located between the magnetic film and a recessed lateral surface of a second substrate. The second substrate is bonded to the first substrate at front surfaces of the first and second substrate. Forming the magnetic film on the planar front allows for patterning of the magnetic film without leaving unwanted residues of magnetic material. Without the unwanted residue of magnetic material, less contamination from the magnetic material is introduced after dry etching and passivation processes, improving yield and reliability of the MEMS device.

Abstract: It is an object to provide a highly reliable semiconductor device with good electrical characteristics and a display device including the semiconductor device as a switching element. In a transistor including an oxide semiconductor layer, a needle crystal group provided on at least one surface side of the oxide semiconductor layer grows in a c-axis direction perpendicular to the surface and includes an a-b plane parallel to the surface, and a portion except for the needle crystal group is an amorphous region or a region in which amorphousness and microcrystals are mixed. Accordingly, a highly reliable semiconductor device with good electrical characteristics can be formed.

Abstract: Semiconductor structures comprising a III-nitride (e.g., gallium nitride) material region and methods associated with such structures are provided. In some embodiments, the structures include an electrically conductive material (e.g., gold) separated from certain other region(s) of the structure (e.g., a silicon substrate) by a barrier material in order to limit, or prevent, undesirable reactions between the electrically conductive material and the other component(s) which can impair device performance. In certain embodiments, the electrically conductive material may be formed in a via. For example, the via can extend from a topside of the device to a backside so that the electrically conductive material connects a topside contact to a backside contact. The structures described herein may form the basis of a number of semiconductor devices including transistors (e.g., FET), Schottky diodes, light-emitting diodes and laser diodes, amongst others.

Abstract: A semiconductor device includes a first gate electrode structure, a second gate electrode structure, a device separation structure, and cell separation structures. The first gate electrode structure is buried in a semiconductor portion in a first cell array at a distance to a first surface of the semiconductor portion. The first gate electrode structure includes parallel array stripes. The second gate electrode structure is buried in the semiconductor portion in a second cell array adjacent to the first cell array. The second gate electrode structure includes parallel array stripes. The device separation structure is between the first and second cell arrays. The device separation structure has a first width. The cell separation structures have at most a second width smaller than the first width and notching, at the first surface, semiconductor fins formed from sections of the semiconductor portion between the array trenches.

Abstract: A light-emitting diode (LED) lighting device includes a substrate, a first bottom electrode, a bottom transparent isolation layer, a first vertical LED, a second vertical LED, a first top transparent electrode, and a second top transparent electrode. The substrate has a first recess therein. The first bottom electrode is disposed in the first recess and is reflective. The first vertical LED and the second vertical LED are disposed in the first recess and on the first bottom electrode. The first bottom transparent isolation layer is disposed in the first recess. The first top transparent electrode is electrically connected to the first vertical LED. The second top transparent electrode is electrically connected to the second vertical LED. The first top transparent electrode, the second top transparent electrode, and the first bottom electrode cooperate to electrically connect the first vertical LED and the second vertical LED in series.

Abstract: A semiconductor device and methods of formation are provided. A semiconductor device includes a dielectric film over a dielectric layer. The dielectric film includes a crystalline structure having a substantially uniform composition of zirconium, nitrogen and oxygen. The dielectric film is formed through in situ nitrogen plasma doping of a zirconium layer. The dielectric film functions as a gate dielectric. The dielectric film has a high dielectric constant between about 28-29 and has a low leakage current density of about 4.79×10?5 A/cm2. The substantially uniform distribution of nitrogen throughout the zirconium oxide of the dielectric film increases the k value of the dielectric film by between about 15% to about 17% as compared to a dielectric film that has a non-uniform distribution of nitrogen through a zirconium oxide layer.

Abstract: Some embodiments include a semiconductor device having a stack structure including a plurality of alternating tiers of dielectric material and poly-silicon formed on a substrate. Such a semiconductor device may further include at least one opening having a high aspect ratio and extending into the stack structure to a level adjacent the substrate, a first poly-silicon channel formed in a lower portion of the opening adjacent the substrate, a second poly-silicon channel formed in an upper portion of the opening, and WSiX material disposed between the first poly-silicon channel and the second poly-silicon channel in the opening. The WSiX material is adjacent to the substrate, and can be used as an etch-landing layer and a conductive contact to contact both the first poly-silicon channel and the second poly-silicon channel in the opening. Other embodiments include methods of making semiconductor devices.

Abstract: A stacked structure includes a first die bonded over a second die. The first die has a first die area defined over a first surface. At least one first protective structure is formed over the first surface, around the first die area. At least one side of the first protective structure has at least one first extrusion part extending across a first scribe line around the protective structure. The second die has a second die area defined over a second surface. At least one second protective structure is formed over the second surface, around the second die area. At least one side of the second protective structure has at least one second extrusion part extending across a second scribe line around the protective structure, wherein the first extrusion part is connected with the second extrusion part.

Abstract: A system and method for manufacturing a through silicon via is disclosed. An embodiment comprises forming a through silicon via with a liner protruding from a substrate. A passivation layer is formed over the substrate and the through silicon via, and the passivation layer and liner are recessed from the sidewalls of the through silicon via. Conductive material may then be formed in contact with both the sidewalls and a top surface of the through silicon via.

Abstract: Methods of dicing semiconductor wafers, each wafer having a plurality of integrated circuits, are described. In an example, a method of dicing a semiconductor wafer having a plurality of integrated circuits involves forming a mask above the semiconductor wafer, the mask including a layer covering and protecting the integrated circuits. The mask is exposed to a plasma treatment process to increase an etch resistance of the mask. The mask is patterned with a laser scribing process to provide gaps in the mask, the gaps exposing regions of the semiconductor wafer between the integrated circuits. Subsequent to exposing the mask to the plasma treatment process, the semiconductor wafer is plasma etched through the gaps in the mask to singulate the integrated circuits.

Abstract: Devices and methods of forming an integrated circuit and a FinFET device with a planarized permanent layer are provided. In an embodiment, a method of forming a planarized permanent layer includes providing a base substrate that has an uneven surface topography. A permanent layer is conformally formed over the base substrate. The permanent layer includes raised portions and sunken portions that correspond to the surface topography of the base substrate. A sacrificial layer is conformally formed over the permanent layer. The sacrificial layer and the raised portions of the permanent layer are chemical-mechanical planarized to provide the planarized permanent layer. The sacrificial layer is substantially completely removed after chemical-mechanical planarizing.

Abstract: Embodiments of the present invention may include a semiconductor patterning method involving forming a fin on a substrate, where the fin may have a sloped sidewall. The fin may be characterized by an initial height and a first width measured proximate a midpoint of the initial height. The method may include forming a masking layer above the fin, and the method may involve removing a first portion of the masking layer. The method may include decreasing the first width of the fin while maintaining the initial height.