Abstract: A method for ensuring CRC error generation by a data communication station after a transmitter exception such as an underrun whereby a parity bit is preset to a binary one, and toggled in response to successive binary ones of a serial bit stream. Each byte of the serial bit stream is transmitted sequentially. If a transmitter exception occurs, the byte before the exception is transmitted normally. However, only the first seven bits of the last byte are transmitted. The parity bit is sent as an eighth bit of the last byte, ensuring odd parity for the previous bit stream. Thereafter, a byte even parity is sent to assure that the overall message has odd parity. A receiving station interprets two consecutive bytes having the predetermined data pattern as the CRC, thus ensuring that the receiving station will reject the frame.

Abstract: A totally self-checking checker checks the faults of a logical circuit and also checks faults inside itself. The totally self-checking checker does not require a large number of gate circuits and minimizes the number of test code words that are used. The code words, of the code word sets to be used, are less than half of all the code words of code since the bits of code Y are divided into M disjoint partial sets.

Abstract: A personal computer has two memory banks respectively connected to two parity check units operative to detect parity errors. Upon doing so, each unit feeds a parity error signal to a separate latch. The latches are connected to a logic circuit which is in turn connected to an interrupt controller that initiates an interrupt when a parity error occurs. One latch is further connected to a check bit of a register of an I/O port and the check bit is set by the one latch. An interrupt handler reads the register and provides messages indicating which memory bank caused the parity error.

Abstract: A method of establishing an inverse pilot sequence for deinterleaving as used in digital transmission, with the interleaving being performed by means of a transmit register and a pilot sequence. Each portion (2 5 1 4 3 6) of the inverse pilot sequence is obtained from the preceding portion (3 1 6 5 4 2) of the inverse pilot sequence and from the two corresponding portions (2 6 1 5 4 3, 4 1 3 6 5 2) of the pilot sequence, with the k-th element of the N-th portion of the inverse pilot sequence being determined by observing the rank of the k-th element in the (N-1)-th portion of the pilot sequence in the N-th portion of the pilot sequence, and then in selecting the element to be found at this rank in the (N-1)-th portion of the inverse pilot sequence.

Abstract: A more secure method for selecting and addressing individual integrated circuit chips and memory locations, registers or input/output ports within the chips includes supplying the chips with address information including address checking information, checking the address information actually received in the chip by using an address checking circuit in the integrated circuit, and inhibiting use of the address information in the chip when the address checking circuit indicates an erroneous address. By inhibiting the use of erroneous address information, state information stored in the integrated circuit is not lost. The integrated circuit sends a fault signal requesting retransmission of the address information for recovery from the address fault. Preferably the address checking information is an error detecting and correcting code for correcting single-bit errors and detecting double-bit errors. Then the integrated circuit functions properly with one defective address input.

Abstract: In an information processor having a central processing unit, a main storage which is accessed by the central processing unit, and an input/output processing unit which controls transfer of information between the central processing unit as well as the main storage and exterior of the information processor; a memory area of the main storage is partitioned into a software area and a hardware area, a train of instructions for inspecting the central processing unit, the main storage and the input/output processing unit are stored in the hardware area, and the central processing unit executes a program stored in the software area and the instruction train stored in the hardware area, alternately at desired intervals so as to decide existence or nonexistence of occurrence of an error on the basis of an executed result of the instruction train.

Abstract: A method of early data frame release using a modified High-level Data Link Control (HDLC) protocol. A destination link station delivers received data frames immediately upon receipt. The data frames are directed to an intelligent application layer with sufficient information to permit resequencing the out-of-order data frames to maintain data synchronization. A transmitter maintains and assigns sequential sequence numbers to each of a plurality of data frames in a radix cycle from zero to seven and back to zero. A transmit toggle bit enables data frame receipt confirmation with the transmitter altering the transmit toggle bit each time the same sequence number is reused. Each data frame must be confirmed before a sequence number can be made available for reuse.

Abstract: A failure analysis system for simulating the effect of a subsystem failure in an electronic system. The failure analysis system includes a knowledge base, a user interface, and a failure analysis component. The knowledge base simulates the electronic system in a variety of operating configurations related to the status of a source selection switching mechanism and/or different system modes. The user interface receives simulation condition data that identifies an operating configuration and failure data identifying at least one subsystem failure. The failure analysis component simulates the propagation of the subsystem failure effect through the electronic system by analyzing the failure data in accordance with the knowledge base and the simulation condition data, and generates a set of subsystem failure responses that would occur in the electronic system if the failure actually occurred. The failure analysis system also performs a fault isolation analysis.

Abstract: Disclosed is a disk controller having an interruptable error correction code circuit for accumulating a remainder during the writing to or reading from data storage media in a disk storage device. An ECC clock latches each bit of data into the circuit when data is being transferred. The ECC clock is controlled by an ECC clock control circuit that monitors sector data and redundancy data transfers to interrupt the ECC clock when sector data transfer is suspended before redundancy data transfer is started. The ECC clock is then allowed to resume after the suspension is complete. Sector data transfer is suspended while the read/write head of the data storage device is passing a defect in the media of the storage device. Since the ECC clock control circuit interrupts the ECC clock while data transfer is suspended, the remainder accumulation will be interrupted while the defect is being passed. While the remainder accumulation is interrupted, the circuit acts as if data is not being transferred during this time.

Abstract: A test architecture in a data processing system having a plurality of circuit portions, coupled via a communication bus. In the system, a dedicated test register is placed in predetermined circuit portions which each can then operate in a normal mode and a test mode. A central processing unit (CPU) may initiate a test operation in any of the circuit portions in response to software executing by writing an operand to a centralized test module. Operands are scanned into and out of a circuit portion being tested while the central processing unit is capable of performing non-test processing activites. The CPU may also test itself using a dedicated test register which can only cause the CPU to enter a test mode after the register is written to.

Abstract: Structures for applying a modification of Tanner's Algorithm B to decode convolutional codes and cyclic and quasi-cyclic error-correcting block codes. The structures comprise one or more parity processors and one or more update processors, wherein the parity equations for a block of code are computed by the parity processors and the reliability of each bit of the result is updated in the update processors using only one register for each bit and without storing received data past the first iteration. The modification to Tanner's Algorithm B is such that each iteration in the updating process is a function only of the results of the immediately previous iteration. A decoder structure receives data serially at a rate of one bit plus soft-decision inormation per clock cycle. The invention is applicable to decoding error-correcting codes used in digital communications.

Abstract: Apparatus to prevent endless switchover attempts between processors in redundant processor systems where each processor resets an associated watch dog timer (WDT). Whenever a WDT times out, WDT sends a restart signal to its associated processor and a failure signal to switchover control logic. The switchover control logic causes a switch from the active processor to the standby processor if the standby processor is healthy and is properly resetting its WDT and, if the standby processor is not, the switchover control logic will generate a signal to cause a cold reboot of the entire system. However, if the standby processor is healthy, the switchover control logic will generate a signal to cause a switchover to the standby and will generate a signal to increment a switchover counter. The value of the switchover counter is compared with a predetermined threshold value.

Abstract: A bit error measuring apparatus in which bit errors in a rewritable information recording medium are measured by reproducing data after the data have been repeatedly recorded on the medium, in which position of recording data used in random number data generated in a memory is periodically shifted every time recording is performed such that not only different recording data can be repeatedly recorded at a predetermined area of the medium at high speed but bit errors can be detected at identical bit locations of the medium by reproducing data from the predetermined area only when the identical recording data have been recorded.

Abstract: An auxiliary direct current electrical power source for protection of a wide variety of DC powered circuits, in particular those of computer systems, upon loss of commercial alternating current (AC) power, to sustain necessary or required functions for the full duration of the ordinary utility company AC power loss. The direct current power source will generally be one or more rechargeable gel cell batteries that are switched directly onto the protected device's internal DC power bus when a loss of AC power is sensed by the present invention. The switch to auxiliary power is inhibited if the protected device was in a manually turned off state at the time of AC loss. At the time of AC power restoral, a time delay ensures that the protected device's own internal power supply will be fully operational before the batteries are switched off the internal DC power bus.

Abstract: Method for quality monitoring of at least two series connected transmission sections in a digital signal transmission link for digital equipment conforming to the synchronous digital hierarchy. Error message bytes in which parity errors are accumulated are transmitted in the section overhead of synchronous transport modules as special bytes for the accumulation of parity errors in successive transmission sections. A quality criterion for the monitored transmission link is acquired from a sequence of error message bytes. The method and the apparatus are advantageously used in transmission equipment of digital synchronous hierarchy.

Abstract: A modem, or data communications device, that is testable independently of a DTE device permits remote testing of it automatically by a network management computer or controller reducing required operator intervention. A data communications network that has possibly hundreds of these modems requires substantially less operator intervention.

Abstract: A data recording/reproducing apparatus can record/reproduce digital data because a parity check code is added to the data at the time of recording. The original data can be reproduced through error correction even though part of the data is lost at the time of reproducing. In the present recording and reproducing apparatus, data immediately after being recorded is read and the number of errors is detected by a parity check code. When the number of errors in the data is equal to or greater than a predetermined reference value, the data is re-recorded in another unit recording area. By setting the reference value at a value less than the maximum number of errors which can be corrected by parity check codes, data can be re-recorded without apprehension that the errors cannot be corrected because the increased number of errors has been caused by deterioration of the recording state of the unit recording area due to repetition of reproducing operations.

Abstract: A test apparatus for data processing and/or editing test data obtained from an object unit to be tested includes, in combination, an organization trade-off element; a failure mode and effect analysis list preparation element, a design review element consisting of a learning section, a knowledge base section and an inference section; a diagnosis rule preparation element; and a data diagnosis element consisting of a knowledge data base section and an inference function section.

Abstract: All elements of a Content-Addressable Memory (CAM) (10) are tested by executing a predetermined set of sequences of the write and match-read operations. During each write operation, a separate one of a set of data words, consisting of the group of all zeros, all ones, a walking ones in a zero word, and a walking zero in a ones word, is written into the CAM for entry in each successive one of its rows of memory cells (14). During each match/read operation, a separate data word from this group is matched to a word stored in each of the rows while, simultaneously, a read operation is performed and the contents of a successive row are read to check for correspondence with a particular data word. A particular set of seven sequences of write and match/read operations is capable of achieving such testing.

Abstract: The present invention relates to a technique for operation on a computer for developing the knowledge base for ultimately providing very fast and cost-efficient fault diagnosis systems. The present technique uses an effective hierarchy of rules where at a first level are rules which allow the arrangement of the system under test to be decomposed into a hierachy of sequential and parallel subsystems. At the second level are rules that generate the efficient testing rules for each pure subsystem. The second level rules can be compared to a node evaluation function in a typical problem of searching a graph to select the best node for expansion from a current list of candidate nodes, so that the best path to the correct system diagnosis is found in the shortest amount of time using a minimum of user input. Two heuristic rules are applied to speed-up the process of selecting the node as the best candidate for expansion.