Abstract: In order to gather, store temporarily and efficiently deliver (if needed) safestore information in a fault tolerant central processing unit having data manipulation circuitry including a plurality of software visible registers, a shadow set of the software visible registers are used in conjunction with shadowing and packing circuitry for copying the contents of the software visible registers, after a data manipulation operation, into the shadow set after the validity of such contents have been verified. In the event of a detected fault in a data manipulation operation, the contents of the shadow set, which will be the last valid set immediately before the error was detected, are transferred back to the software visible registers to institute recovery at the point in the data manipulation immediately prior to that at which the error was detected.

Abstract: Plural embedded servo sector sets are written as a single operation by a servo writer during manufacture of a hard disk drive. Later, the disk drive electronics performs a self scan and selects one good set of embedded servo sectors and erases all other sets, thereby decreasing the number of servo sector rewrites during manufacture and reducing manufacturing time and costs.

Abstract: A codeword forcing technique is applied which provides gradual degradation of an audio output during fading such that analog degradation in a fading signal environment is simulated.

Abstract: A correction of microprocessor chip design errors is achieved by identifying selected sets of instructions and/or selected sets of instruction sequences in an erroneous control flow of the microprocessor and/or by identifying selected sets of interface control and status signals. A match selectively initiates a corrective action by interfering with the instruction flow in the microprocessor chip or by requesting external control from an associated processor unit. Alternatively, a match is used for a programmable modification of interface control and status signals to adapt the chip to changes of its environment without redesign.

Abstract: A lock-up prevention circuit and method are used with a watchdog timer circuit. The lock-up prevention circuit includes a logic circuit for receiving a first signal for generating an enabling signal, and responds to a first predetermined bit stored in a control register for controlling a loading of an enabling signal to the control register. The watchdog timer circuit responds to the loading of the enabling signal to be enabled to respond to a second predetermined bit of the control register for controlling initiation of a timing cycle of the watchdog timer circuit. In response to a clock signal and a second predetermined bit of the control register, the logic circuit clocks the control register to load the enabling signal.

Abstract: A limited multi-fault system and method manages error recovery in a local area network system. The system includes a data structure which store related error events, diagnostic problems and causes. In addition, a method of managing error events in real time and identifying causes and recommending actions is provided. A knowledge base is used to determine the causes and recommended actions for the problem.

Abstract: A convolutional interleaver and addressing scheme where up to B consecutive symbols containing errors can be interleaved such that they are separated from each other by at least N intervening symbols. Memory, such as RAM, is configured with (B-1) cells of increasing size for storing symbols from a data stream. A first one of the cells has M storage locations which store M symbols. Each successive one of the cells has M more storage locations than the immediately preceding cell for storing M more symbols than the immediately preceding cell, where M=N/B. The cells are successively addressed to write a next symbol from the stream into a next write symbol location in a currently addressed cell and to read a symbol from the location of the currently addressed cell immediately following the next write symbol location. The locations are accessed in a first revolving manner such that the last location in a cell is followed by the first location in that cell.

Abstract: A memory controller parity system that detects both even and odd bit errors in memory addresses and global errors in memory data. The parity system detects errors in any memory system employing an address bus or data allocation map. It is effective for applications requiring random memory accesses as well as in blocked-data accesses such as in controller buffer memories for servicing disk file systems and tape storage systems. The controller stores data in memory together with a single appended global parity bit representing (n-1) bits from an n-bit address, thereby detecting both even and odd fixed errors over time. A p-bit identification register can be added to the controller to facilitate detection over time of global data errors arising from data allocation map errors during the data storage period. The single-bit parity scheme is compatible with existing single-bit parity memory systems.

Abstract: A SRAM testing circuit utilized to assure that a voltage is at a sufficient level for accessing a memory cell including a pair of memory cells each including those elements necessary to duplicate the memory cells of an associated memory array, a circuit for providing alternating-valued input signals for writing to the pair of memory cells during each clock period at which a write operation may occur, apparatus for emulating the load provided to a bitline of an associated memory array, apparatus for applying the input signals to one of the pair of memory cells and applying the inverse of the input signals to the other of the pair of memory cells, apparatus for testing both the condition of each of the memory cells after the application of the input and inverse input signals against the condition of the signals provided to each of the cells to determine if each of the pair of memory cells has switched to the appropriate condition, and apparatus for generating a fail signal if either one of the pair of memory ce

Abstract: A fault tolerant protocol for determining the beginning of data despite the presence of burst errors in a frame of transmitted data. The fault tolerant protocol of the present invention provides in the frame of transmitted data a plurality of different preamble characters, P, in a prearranged order before the beginning of data. The frame of transmitted data before the plurality of preamble characters is a plurality of identical synchronization characters, S. The protocol of the present invention detects a predetermined number, n, of sequential synchronization characters in the plurality, s, of synchronization characters. Upon detection, a synchronization signal is issued indicating acquisition of synchronization. Upon receipt of the synchronization signal, the invention detects a majority, m, of preamble characters in the plurality of preamble characters. When a majority of the preamble characters have been detected, the beginning of data is determined.

Abstract: A system for testing circuits of digital data telecommunications networks provides selected physical and protocol testing on an integrated basis. Systems and test methods provide for analysis of test results to provide diagnosis of probable cause of actual or apparent faults related to data transmission and may also provide automatic implementation of additional diagnosis, followed by a second level of fault diagnosis using the additional test results. Display screens provide the results of fault analysis, provide comparative viewing of fault-free benchmark data and provide suggestions as to probable cause of faults. A central test unit portion of the system may be installed at a carrier's offices and testing may be controlled on a dial-up basis over telephone lines from a remote customer location using a personal computer as the test selection entry and information screen viewing device.

Abstract: A new class of error detection codes has powerful error detection properties, as well as significant implementation advantages. The inventive error detection codes are used in communication protocols to protect transmitted data from corruption.

Abstract: A universal pattern generator generates a digital signal pattern. The generator includes a user programmable device for specifying a repeatable digital signal pattern. The programmable device allows for the selection of a framing structure having a number of channels. The programmable device also has input means for inputting data into the channels of the framing structure. A data set representing the repeatable digital signal pattern is generated. The data set is held in memory. A transmitter responsive to the data set held in memory repeatably transmits the repeatable digital signal pattern represented by said data set.

Abstract: A sync interpolative circuit and sync state detecting circuit for use in a disc reproducing apparatus, which reproduces data by generating an interpolative sync signal even when a sync pattern of reproduced data is changed or no sync signal exists. The sync interpolative circuit generates the interpolative sync signal for accurately reproducing desired data, and the sync state detecting circuit informs a controlling portion of a state of the sync signal detected from the disc to facilitate data processing in the sector unit, thereby providing for more accurate reproduction of data regardless of errors in the sync signal.

Abstract: A bus architecture and associated circuitry for providing communication between processors and multiple gate arrays whereby the size of the data being transferred may be either full words of 32-bits or 36-bits per word, or half words of 16-bits or 18-bits per word. Parity generation logic operates on the data to be sent over the bus to generate a parity value from the correct data bits depending on the selected data word size. Parity checking logic operates on the data received from the bus to check the parity of the correct data bits depending on the selected data word size.

Abstract: An interrupt processor controller (IPC) through which all interprocessor interrupts are routed in a complex integrated circuit. For processors which receive external interrupts, the interrupt processor controller may receive those interrupts and route those as well to the particular processor. The IPC includes interrupt routing logic which determines when a subsequent interrupt will cause an error condition with a previously instigated interrupt that has not been cleared. When such a condition occurs, a bit is set in an error detect register that is coupled to the interrupt routing logic. All of the bits of the error detect register are logically OR'ed, the output of which is routed to a single dedicated pin for indicating an interrupt error condition has occurred. This pin may have its signal routed back into the complex integrated circuit for signaling a trap handler or some other mechanism that an interrupt error condition has occurred.

Abstract: An Asynchronous Transfer Mode (ATM) cell error processing system includes a plurality of error detectors for respectively detecting predetermined cell errors and for respectively generating decision signals and an error editing unit which is operatively coupled to the error detector and determines, based on the decision signals, whether or not a cell related to the decision signals should be discarded. A buffer, which is coupled to at least one of the error detectors, temporarily stores the cell. An error cell discarding unit, which is coupled to the error editing unit and the buffer, discards the cell from the buffer when the error editing unit determines that the cell should be discarded and relays the cell when the error editing unit determines that the cell should not be discarded.

Abstract: Apparatus, operating in a digital communication system, for interconnecting a primary or a secondary network to an output port. The primary and secondary networks are redundant networks having point-to-point topologies (125, 130) or point-to-multi-point topologies (210, 215). When connected in a point-to-point network topology that supports extended superframe format (ESF), the apparatus functions as an error correction switch and; when connected in a point-to-multi-point network topology, the apparatus functions as a DS1/0 protection switch. In its receiver aspect, the apparatus stores frames of digital data received from each of two redundant networks, inspects certain error codes contained in the received data and, in response to these error codes, selects the digital data originating from one of the networks that does not exhibit an error code. The data selection process uses a time-slot interchanging (TSI) technique.

Abstract: A remote data shadowing system provides storage based, real time disaster recovery capability. Record updates at a primary site cause write I/O operations in a storage subsystem therein. The write I/O operations are time stamped and the time, sequence, and physical locations of the record updates are collected in a primary data mover. The primary data mover groups sets of the record updates and associated control information based upon a predetermined time interval, the primary data mover appending a prefix header to the record updates thereby forming self describing record sets. The self describing record sets are transmitted to a remote secondary site wherein consistency groups are formed such that the record updates are ordered so that the record updates can be shadowed in an order consistent with the order the record updates cause write I/O operations at the primary site.

Abstract: The extended error correction process of the present invention error corrects a data message that has been transmitted a plurality of times. The process first receives the data message at least twice, logically combining the first and second messages received to form an error indication word. The error indication word is then used to locate the error locations in each message after which some of the errors are complemented, depending on the total number of errors found. The message is then decoded and used for transmit power changes, channel reassignment, to release a call, etc.