Abstract: A cloning technique enables efficient and substantially instantaneous creation of a clone that is a writable copy of a “parent” virtual volume (vvol) in an aggregate of a storage system. A base snapshot is provided from the parent vvol. In addition, a new vvol is created, along with a new file system identifier, a new subdirectory in the aggregate and a new storage label file. The new vvol is embodied as a clone and comprises an appropriately sized container file, wherein initially the container file has no data. Moreover, a volume information (volinfo) block for the clone is created that is a slightly modified version of the volinfo block from the base snapshot; the modified volinfo block is written to the container file. The clone is then instantiated by loading a file system associated with the new vvol onto the clone and bringing the clone “online”.

Abstract: In one embodiment, the present invention is directed to a system processing memory transaction requests. The system includes a controller for storing and retrieving cache lines and a buffer communicatively coupled to the controller and at least one bus. The controller formats cache lines into a plurality of portions, implements an error correction code (ECC) scheme to correct a single-byte error in an ECC code word for pairs of the plurality of portions, stores respective pairs of plurality of portions such that each single-byte of the respective pairs of the plurality of portions is stored in a single one of a plurality of memory components. When the controller processes a memory transaction request that modifies tag data without modifying cache line data, the buffer calculates new ECC data utilizing previous ECC data, previous tag data, and the new tag data without requiring communication of cache line data.

Abstract: Provided are a method, system, and program for translating virtual addresses of memory locations within pages of different sizes. In one embodiment, a translation entry containing a physical address is stored in a data structure table for each page. Each virtual address includes a page virtual address which identifies the translation entry containing the physical address of the page containing the memory location. The virtual address may be translated to a translation entry index using the size of the page containing the memory location.

Abstract: A disk array device having a dual controller for executing data input/output processing for disk drives in response to a data input/output request from a host computer. Each controller constituting the dual controller has an FC controller which is interface-connected to the host computer via one path of a front interface connection FC and to the disk drives via one path of a back interface connection FC, and a PBC for switching the connection destination of the back interface connection FC between the two FC-ALs loop-connected to the disk drives.

Abstract: Described herein are a method and system for memory access. As the complexity of digital signal processing applications increases, designs may require multiple memory chips. To optimize the bandwidth of the data being accessed from the memory chips, blocks of data are read alternatively from each memory chip. The size of a block of data is determined by the bit width of a word and the number or memory arrays in a chip.

Abstract: Interleaver for iterative decoder. A memory management scheme allows for single plane/single port memory devices to be used by the interleaver. The design is adaptable to soft-in soft-out (SISO) decoders that perform iterative decoding. The interleaver may be implemented within communication devices that implement two distinct SISOs that operate cooperatively or within communication devices that employ a single SISO (in a recycled embodiment) that functionally performs the analogous decoding operations that would be performed by the two distinct SISO implementation. The use of single plane/single port memory devices by the interleaver allows for a great deal of savings from many perspectives: the sizes of the required interleaver memory and the interleaver pattern memory are both cut in half using this approach, and a cost savings may also be realized, in that, cheaper, slower memories may be used since each respective interleaver memory is read only every other cycle.

Abstract: A integrity control system uses the address bits to enable protection of data stored in a system memory. An address bus that determines the location of data to be stored or retrieved from system memory has a plurality of address lines. A subset of the address lines enables the protection mechanism to generate an integrity control value representative of the data and determine where the integrity check value is stored in a secure memory.

Abstract: A memory management system and method. The system includes a first storage device and a processing unit. The first storage device stores an exception code excluding operation codes (op-codes) corresponding to an instruction set. The processing unit reads the exception code from the first storage device and writes it to at least one unoccupied region of a memory in an electronic device, thereby enabling the electronic device to stop program execution when the CPU fetches the exception code from the unoccupied region of the memory.

Abstract: A node includes a processor coupled to an interconnect and a memory bridge coupled to the interconnect. The processor is configured to maintain a first indication of whether or not a modification of data at a first address has been detected by the processor after a most recent load-linked (LL) instruction was executed by the processor to the first address. The memory bridge is responsible for internode coherency within the node, and is configured to initiate a first transaction on the interconnect in response to receiving a probe command from another node. The processor is configured, during a time period in which the processor has a second transaction outstanding to the first address, to change the first indication to the first state responsive to the first transaction.

Abstract: A system and method creates a writable clone of a read-only volume. A base snapshot is generated on a source volume on a source storage system and is duplicated as a read-only base snapshot replica on a target volume on a destination storage system. A copy (“clone) is then substantially instantaneously created from the read-only base snap-shot replica, thereby creating a writable clone of a read-only volume.

Abstract: A clone splitting technique enables efficient online splitting of blocks shared between a parent virtual volume (vvol) and a clone in accordance with a shared block splitting procedure executing on a storage system. Online splitting of shared blocks denotes allowing execution of read/write operations directed to the clone, as well as to the parent vvol, as the shared blocks are split. The clone splitting technique removes any connection between a clone and its parent vvol, thereby allowing the clone to be used as a first-class volume. Moreover, the technique removes such connection while allowing both the clone and parent vvol to remain available online and writeable (accessible) to clients during the shared block splitting procedure.

Abstract: A data storage device architecture includes a HDA printed circuit board (PCB) including a spindle motor driver, a read/write arm driver, a read channel driver, and a first input/output (I/O) interface that are arranged on the HDA PCB. An application PCB includes at least one of an application specific integrated circuit and a processor that performs application and hard drive control related processing. A buffer stores application and hard drive control related data. A hard drive controller (HDC), a mapping driver, and a second I/O interface are arranged on the application PCB. The second I/O interface communicates with the first I/O interface. The mapping driver is capable of at least one of mapping logical addresses to physical addresses and monitoring a location of a read/write head.

Abstract: A method and apparatus for aggregating storage devices is disclosed. A package for providing high density storage uses a carrier housing for holding multiple storage devices proximate to one another and aligned in a row, and an access device, coupled to the carrier housing, aggregates the physical addresses of the storage devices into logical addresses and making the logical addresses available over a connection.

Abstract: A method and apparatus for providing high-density storage is disclosed. A plurality of storage devices is aggregated in a package. A package-level controller is coupled to a carrier housing holding a plurality of storage devices, wherein the package-level controller provides a RAID logical configuration at a package-level for the storage devices held in the carrier housing. A controller may also be provided for virtualizing the logical addresses as at least one aggregate volume to provide a layer of abstraction to the storage devices. The package may be inserted into a storage system designed to manage multiple packages.

Abstract: The disclosure is a NAND flash memory with the function of error checking and correction during a page copy operation. The NAND flash memory is able to prohibit transcription of erroneous bits to a duplicate page from a source page. Embodiments of the inventive flash memory include a correction circuit for correcting bit errors of source data stored in a page buffer, a circuit configured to provide the source data to the correction circuit and to provide correction data to the page buffer, and a copy circuit configured to copy the source data to the page buffer, and to store the correction data in the other page from the page buffer.

Abstract: The present invention provides a method for a processor to write data to a cache or other fast memory, without also writing it to main memory. Further, the data is “locked” into the cache or other fast memory until it is loaded for use. Data remains in the locking cache until it is specifically overwritten under software control. The locking cache or other fast memory can be used as additional system memory. In an embodiment of the invention, the locking cache is one or more sets of ways, but not all of the sets or ways, of a multiple set associative cache.

Abstract: A computer system and method for efficient storage and retrieval of data. The inventive computer system may comprise means for storing data, wherein data are allocated to predetermined categories that are components of at least one stored categorical structure forming an object model, wherein attributes that are inherited within the categorical structure are allocated to the categories; at least one inquiry unit for making queries relating to the stored data; and at least one inference unit used to evaluate declarative rules linking at least one of said categories and said attributes.

Abstract: The present invention provides a method of storing data transferred from an I/O device, a network, or a disk into a portion of a cache or other fast memory, without also writing it to main memory. Further, the data is “locked” into the cache or other fast memory until it is loaded for use. Data remains in the locking cache until it is specifically overwritten under software control. In an embodiment of the invention, a processor can write data to the cache or other fast memory without also writing it to main memory. The portion of the cache or other fast memory can be used as additional system memory.

Abstract: Processor-based systems may use more than one software routine or method to access a write-back cache. If the methods are inconsistent, the data in the write-back cache may be incoherent with a disk drive that is being cached. A method and apparatus for preserving coherent data in a write-back disk cache may include writing dirty cache lines to a disk drive and monitoring for disk write requests, prior to a disk driver loading.

Abstract: A method of operating a memory device includes placing the memory device in a persistent auto precharge mode of operation, applying a disable command to the memory device, and disabling the persistent auto precharge mode of operation in response to the applied disable command. Memory devices operating according this method may be used in memory systems that infrequently experience page hits, such as server systems, while the ability to disable the persistent auto precharge mode allows such memory devices to be used in systems that frequently experience page hits, such as graphics or input/output applications.