Abstract: An apparatus and a system, as well as a method and article, may operate to control a bandwidth of a memory coupled to a plurality of data processing units responsive to protocol indications, such as a number of data processing units in use. In some embodiments, apparatus and systems, as well as methods and articles, may operate to select a memory access group size of about 2N memory banks responsive to receiving an indication of a change in a protocol type, wherein the group is selected from a number B of banks, and N is associated with the protocol type.
Abstract: In a novel snapshot management method for a data storage system which does not use duplication (mirroring), when a snapshot of a main volume pertaining to a designated time is being taken, every time a write request to a storage region in the main volume is received, if the data in that storage region has not been copied to an auxiliary volume since the designated time, that data is copied to the auxiliary volume, and the writing to the storage region is carried out after that. In the case of sequential writing, also for data in a further storage region, following the target storage region, on which it is predicted that sequential writing will be carried out henceforth, if copying to the auxiliary volume has not been carried out since the designated time, the data is copied to the auxiliary volume in the same way.
Abstract: Content addressable data storage and compression for semi-persistent computer memory including providing a chunk of data that is a quantity of input data; retrieving a memory block from semi-persistent computer memory; searching for a segment of the chunk that matches the memory block; and if a matching segment is found: discarding the matching segment; providing a retrieval key for the memory block as a retrieval key for the matching segment; identifying an unmatched portion of the chunk that does not match the memory block; identifying a free memory block of a file system; storing the unmatched portion semi-persistently in the free memory block; and providing a retrieval key for the unmatched portion.
Type:
Grant
Filed:
December 3, 2003
Date of Patent:
November 7, 2006
Assignee:
International Business Machines Corporation
Abstract: A memory controller may be implemented using dynamic page conflict prediction to control the closure of memory pages. A memory controller may include a page history register configured to store a value indicating the pattern of page conflicts encountered by a memory device. The memory controller may include a global conflict predictor for storing probabilities of page conflicts associated with values of the page history register. In response to receiving a memory access request, a control unit may be configured to determine whether the memory access request causes a page conflict. The memory controller may be configured to update the global conflict predictor based on this determination. If a page conflict is predicted, the memory controller may automatically close the targeted page (e.g., by initiating the memory access in auto-precharge mode) upon completion of the memory access requested by the memory access request.
Abstract: An redundant array of independent disks (RAID) storage device is provided. The RAID comprises M number of storage devices, and the storage blocks of the same J-column in each storage device comprises complete stripe blocks and at least a plurality of partially complete stripe blocks. Inside the same stripe block, the total number of the storage blocks (L) is smaller than the number of the storage device (M), and the quantity of the storage blocks (M) is not multiple of storage blocks (L).
Abstract: Provided are a method, system, and article of manufacture for copying storage. Copy operations are performed on source storage units to copy to target storage units, wherein the copy operations create a consistent copy of the source storage units in the target storage units. While performing a copy operation to copy from one source storage unit to one target storage unit, a write operation is restricted from being performed on the one source storage unit, until the copy operations have been performed on the source storage units.
Type:
Grant
Filed:
June 18, 2003
Date of Patent:
November 7, 2006
Assignee:
International Business Machines Corporation
Inventors:
Sam Clark Werner, William Frank Micka, Sivan Tal, Ifat Nuriel, Sheli Rahav, Gail Andrea Spear, Warren K. Stanley
Abstract: A memory tag mechanism creates a logical memory tag of a first length that corresponds to an I/O address of a second length. The memory tag is “logical” because it does not represent physical memory. When an I/O adapter device driver that expects an address of the first length is invoked, the memory tag is passed. When the I/O adapter device driver makes a call to the partition manager to convert the address of the first length (i.e., memory tag) to an I/O address of the second length, the partition manager detects that the passed address is a memory tag instead of a real address, and returns the corresponding I/O address. In this manner existing device drivers that expect addresses of the first length may be used for redirected DMA, which allows performing DMA operations directly from a shared I/O adapter in a hosting partition to memory in a hosted partition.
Type:
Grant
Filed:
March 31, 2004
Date of Patent:
October 31, 2006
Assignee:
International Business Machines Corporation
Inventors:
David Charles Boutcher, Colin Robert DeVilbiss, David Robert Engebretsen
Abstract: Techniques to assure genuineness of data stored on a storage device are provided. The storage device includes a storage controller that conducts I/O operations and management operations. A description of management operations and corresponding timestamps are recorded to an operation log stored in a memory. The memory additionally stores an attribute for each storage volume of the storage device. Write access to each of the storage volumes is dependent on the attribute.
Abstract: In a substrate structure of a primary disk array apparatus of a disk array system, the primary disk array apparatus contains in one housing at least a plurality of disk drives and a controller substrate with a controller section for controlling the disk drives, and a resource management section that is mounted on the controller substrate of the primary disk array apparatus for managing resources within the housing.
Abstract: Embodiments of the present invention provide an algorithm for scheduling read and write transactions to memory out of order to improve command and data bus utilization and gain performance over a range of workloads. In particular, memory transactions are sorted into queues so that they do not have page conflict with each other and are scheduled from these queues out of order in accordance with read and write scheduling algorithms to optimize latency.
Type:
Grant
Filed:
October 22, 2003
Date of Patent:
October 24, 2006
Assignee:
Intel Corporatioon
Inventors:
Hemant G. Rotithor, Randy B. Osborne, Nagi Aboulenein
Abstract: A method is provided for improving the performance of copy operations in storage systems. The method includes storing a measure of relative availability of storage system resources, detecting operations when sequential portions of a storage media are to be accessed for writing of information, and when the measure of relative availability of system resources drops to a specified extent, introducing a wait into the operation in which sequential portions of a storage media are to be accessed for writing of information. In another implementation, a method is provided for controlling writing of data in a storage system in which a step is performed of analyzing a requested write operation to determine if the requested write operation calls for a sequential task or a random task. If the requested write operation is a sequential task, information about it is stored in a task management table.
Abstract: Under a hetero-environment in which different sorts of disk-systems are mixed with each other, a data guaranteeing operation can be carried out. When a cache controller of a local disk system receives a data writing request from a host computer the cache controller stores data into a local disk provided in a disk device group. The data received from the host computer is also transmitted to a remote disk system, and is stored in a remote disk. The data stored in the remote disk is immediately read and the data written in the remote disk is compared with the data written in the local disk. As a result, since a data guarantee operation on the remote side is processed by the local disk system instead of the remote disk system, a data guaranteeing operation when a remote copying operation is performed can be carried out even in the storage system under a hetero-environment.
Abstract: Apparatus and method for emulating a virtual machine within the physical memory space of a programmable processor using virtual functions having a format independent of the hardware architecture of the processor. The virtual functions are executed using an execution engine emulated in the processor. A symbol table maps the virtual functions to native functions in the memory space, and a gate call interface block accesses the symbol table and initiates execution of the corresponding native function in response to each executed virtual function. Execution of the corresponding native function operates to evaluate the concurrent execution of at least one other native function. In this way for example, standardized platform virtual code can be generated for a number of different types of processors and used to evaluate the native operational routines of each processor.
Type:
Grant
Filed:
October 3, 2003
Date of Patent:
October 17, 2006
Assignee:
Seagate Technology LLC
Inventors:
Chad R. Overton, Sunil A. Mehta, John M. Larson, Scott E. Errington
Abstract: A method of operating a memory device includes placing the memory device in a persistent auto precharge mode of operation, applying a disable command to the memory device, and disabling the persistent auto precharge mode of operation in response to the applied disable command. Memory devices operating according this method may be used in memory systems that infrequently experience page hits, such as server systems, while the ability to disable the persistent auto precharge mode allows such memory devices to be used in systems that frequently experience page hits, such as graphics or input/output applications.
Abstract: Critical sections of multi-threaded programs, normally protected by locks providing access by only one thread, are speculatively executed concurrently by multiple threads with elision of the lock acquisition and release. Upon a completion of the speculative execution without actual conflict as may be identified using standard cache protocols, the speculative execution is committed, otherwise the speculative execution is squashed. Speculative execution with elision of the lock acquisition, allows a greater degree of parallel execution in multi-threaded programs with aggressive lock usage.
Abstract: It is an object to eliminate possibilities in which newest backup data cannot be created owing to overwriting of data update records when performing backup using a duplicating system. The data backup system, including an active system as a computer system of a backup source and a standby system as a computer system of a backup destination, is provided in such that a communication settings judging section is provided in the standby system for actively changing settings of a data communicating section for transferring data update records to thereby prevent overwriting of portions among data update records that are necessary for creating newest backup data.
Abstract: Integrated search engine devices include a content addressable memory (CAM) core that is configured to support at least one database of searchable entries therein and a control circuit. The control circuit is configured to support reporting to a command host of data identifying entries that have been aged out of the at least one database and/or entries that have exceeded an activity-based aging threshold. The control circuit is further configured to support age reporting that is programmable on a per entry basis within the at least one database.
Type:
Grant
Filed:
November 14, 2003
Date of Patent:
October 10, 2006
Assignee:
Integrated Device Technology, Inc.
Inventors:
John R. Mick, Jr, Harmeet Bhugra, Jakob Saxtorph
Abstract: A method and apparatus for managing overlay data requests are disclosed. One embodiment of an apparatus includes a request unit and a timer. A request is made by a graphics controller to the request unit for a line of overlay data. The request unit divides the request from the graphics controller into a series of smaller requests. The smaller requests are issued to a memory controller. Delays are inserted between each of the smaller requests in order to allow other system resources to more easily gain access to memory.
Type:
Grant
Filed:
September 26, 2003
Date of Patent:
October 10, 2006
Assignee:
Intel Corporation
Inventors:
Todd M. Witter, Aditya Sreenivas, Kim Meinerth
Abstract: A method and apparatus for efficient runtime memory access in a database is provided. A buffer pool is pre-allocated in cache. Buffers in the buffer pool are sized to accommodate average case queries and frequently executed queries. Buffers from the buffer pool are allocated to query working sets during runtime to reduce cache misses.
Abstract: According to an embodiment, a content addressable memory (CAM) device (104) may be capable of executing a “restricted” search operation. A restricted search operation (an “explore” or “search beyond” operation) may compare only a portion of the CAM entries to a search key device. Preferably, a restricted search operation may restrict searches to entries having an index value greater than a received search index value.
Type:
Grant
Filed:
October 28, 2002
Date of Patent:
October 3, 2006
Inventors:
David V. James, Jagadeesan Rajamanickam, Michael C. Stephens, Jr.