Abstract: Embodiments of an invention for address translation for scalable I/O device virtualization are disclosed. In one embodiment, an apparatus includes PASID table lookup circuitry. The PASID table lookup circuitry is to find a PASID-entry in a PASID table. The PASID-entry is to include a PASID processing mode (PPM) indicator and a first pointer to a first translation structure. The PPM indicator is to specify one of a plurality of translation types, the one of the plurality of translation types to use the first translation structure.

Abstract: A Non-Volatile Dual In-Line Memory Module is disclosed (NVDIMM). The NVDIMM may be installed in a Dual In-Line Memory Module (DIMM) docket. The NVDIMM may include a non-volatile memory. A device driver may intercept a request for a memory address destined for a host memory controller, replace the memory address with a pre-mapped memory address or an alias of the pre-mapped memory address, and send the pre-mapped memory address to the host memory controller, so that the host memory controller generates a target memory address to NVDIMM.

Abstract: A memory device includes a memory, and a processor coupled to the memory and configured to hold memory information corresponding to the memory, access information corresponding to access to the memory, and storage information indicating a storage area of the access information, extract, based on the storage information, an access information code including the access information, output the memory information in response to a read request from an external, and output the extracted access information code in response to an acknowledgment received from the external corresponding to the memory information.

Abstract: Adaptively changing a fail bit count for an erase operation is disclosed. A memory system may detect an erase stuck bit condition in a group of memory cells. An erase stuck bit condition refers to a situation in which the threshold voltage of at least one memory cell on string tends to stick, such that the string cannot be erased. The memory system performs an action in response to detecting an erase stuck bit condition, in one embodiment. One possible action is to increase a fail bit count for erase operations for other groups of memory cells, which could also potentially suffer from erase bit stuck conditions. This can help reduce erase stress on groups of memory cells. It can also reduce the number of groups of memory cells that need to be retired for failing an erase operation.

Abstract: The present disclosure includes apparatuses and methods for cache operations. An example apparatus includes a memory device including a plurality of subarrays of memory cells, where the plurality of subarrays includes a first subset of the respective plurality of subarrays and a second subset of the respective plurality of subarrays. The memory device includes sensing circuitry coupled to the first subset, the sensing circuitry including a sense amplifier and a compute component. The first subset is configured as a cache to perform operations on data moved from the second subset. The apparatus also includes a cache controller configured to direct a first movement of a data value from a subarray in the second subset to a subarray in the first subset.

Abstract: Enabling a prefetch request to be controlled in response to conditions in a receiver of the prefetch request and to conditions in a source of the prefetch request. One or more processors identify, based on a prefetch tag, a prefetch request that is associated with a prefetch instruction that is executed by a remote processor. The one or more processors generate the prefetch request in a remote processor according to a prefetch protocol. The prefetch request includes i) a description of at least one prefetch request operation and ii) a prefetch request information. A local processor, of the one or more processors, receives the prefetch request from the remote processor.

Abstract: Aspects of managing Translation Lookaside Buffer (TLB) units are described herein. The aspects may include a memory management unit (MMU) that includes one or more TLB units and a control unit. The control unit may be configured to identify one from the one or more TLB units based on a stream identification (ID) included in a received virtual address and, further, to identify a frame number in the identified TLB unit. A physical address may be generated by the control unit based on the frame number and an offset included in the virtual address.

Abstract: Enabling a prefetch request to be controlled in response to conditions in a receiver of the prefetch request and to conditions in a source of the prefetch request. One or more processors identify, based on a prefetch tag, a prefetch request that is associated with a prefetch instruction that is executed by a remote processor. The one or more processors generate the prefetch request in a remote processor according to a prefetch protocol. The prefetch request includes i) a description of at least one prefetch request operation and ii) a prefetch request information. A local processor, of the one or more processors, receives the prefetch request from the remote processor.

Abstract: A nonvolatile memory system includes: a nonvolatile memory device that includes a nonvolatile memory cell array and a page buffer; and a memory controller that loads into the page buffer mapping data that is stored in the nonvolatile memory cell array, and in response to a logical address received from outside the memory controller, translates the logical address into a physical address based on the mapping data that is loaded into the page buffer.

Abstract: In one embodiment, a memory control process of a device receives a plurality of program/erase (P/E) requests for a flash memory of the device. The memory control process then stores data associated with the plurality of P/E requests in a random access memory (RAM) of the device, and aggregates the plurality of P/E requests into a single P/E operation. The memory control process may then send the single P/E operation to the flash memory at a given interval to update the flash memory with the data stored in the RAM.

Abstract: A computing device receives, at a scheduler of the computing device, a first write request from a first thread of a plurality of threads. The scheduler schedules access for the plurality of threads across a boundary of an access-controlled region in a memory of the computing device. The computing device determines that a second memory region in the access-controlled region is allocated for storing data copied from a first memory region. During copying, to the second memory region, the data copied from the first memory region, the computing device permits scheduling, by the scheduler, an operation to read from the first memory region for any read requests from the plurality of threads during the copying; and denies scheduling, by the scheduler, an operation to write to the first memory region for any subsequent write requests from the plurality of threads during the copying.

Abstract: According to one embodiment, a system includes a first electronic apparatus and a second electronic apparatus. The first electronic apparatus causes an external storage medium to store first information which controls possibility of writing of a file to the external storage medium in units of file. The second electronic apparatus determines possibility of the writing of a requested file to the external storage medium based on the first information, write the requested file to the external storage medium if the requested file is determined to be capable of being written, and prohibit the writing of the requested file to the external storage medium if the requested file is determined to be incapable of being written.

Abstract: In one aspect of the present disclosure, a method involves obtaining, by a body-mountable device, sensor data, where the body-mountable device includes a data storage. The method further involves making a determination that each condition in a condition set has been satisfied. In addition, the method involves responsive to making the determination that each condition in the condition set has been satisfied, storing the obtained sensor data in the data storage.

Abstract: Disclosed herein are embodiments for free-space handling in pages and in-memory containers allowing variable-size data entries. An example system may determine expanses of unallocated space, within a page loaded in memory and configured to allocate a first data entry of a first size within the page that may also allocate at least one subsequent data entry of a second size different from the first size; save, into memory, transient free-space information corresponding to the page, including first position information for a first number of expanses of contiguous unallocated space within the page; evict the page from memory, writing allocated data entries contained therein to persistent storage; store, into persistent storage, persistent free-space information corresponding to the page, including second position information for a second number of expanses of unallocated space within the page, the second number being less than the first number; and discard the transient free-space information.

Abstract: Cache logic for generating a cache address from a binary memory address comprising a first binary sequence of a first predefined length and a second binary sequence of a second predefined length, the cache logic comprising: a plurality of substitution units each configured to receive a respective allocation of bits of the first binary sequence and to replace its allocated bits with a corresponding substitute bit string selected in dependence on the received allocation of bits; a mapping unit configured to combine the substitute bit strings output by the substitution units so as to form one or more binary strings of the second predefined length; and combination logic arranged to combine the one or more binary strings with the second binary sequence by a reversible operation so as to form a binary output string for use as at least part of a cache address in a cache memory.

Abstract: A storage system performs transformations of data stored as source snapshots to obtain transformed snapshots. The storage system stores relations between source snapshots, for example, parent child relationships. The storage system analyzes relationships between source snapshots to determine relationships between transformed snapshots. The storage system creates a transformed snapshot based on a source snapshot. The storage system traverses the graph representing source snapshots to identify ancestor or descendants of the source snapshots that were previously transformed. The storage system determines the transformed snapshots corresponding to the ancestor and descendant source snapshots and relates them to the newly created transformed snapshot.

Abstract: Processors configured by aspects of the present invention optimize reference cache maintenance in a serialization system by serializing a plurality of objects into a buffer and determining whether any of the objects are repeated within the buffered serialized plurality. The configured processors insert an object repetition data signal within the serialized plurality of objects that indicates to a receiver whether or not any objects are determined to be repeated within the buffered serialized plurality of objects, and send the serialized plurality of objects with the inserted object repetition data signal as a single chunk to a receiver, wherein the inserted object repetition data signal conveys reference cache management instructions to the receiver.

Abstract: Techniques are disclosed which allow a secondary storage system to provide data to non-production workloads in conjunction with performing data backup and protection tasks. As disclosed, a secondary storage system exposes backup data stored by the secondary storage system to other workloads, such as test and development applications, data analytics, etc. These non-production workloads can run at the same time the secondary storage system provides backup services to a primary storage system. This consolidation eliminates the need for an enterprise to deploy separate storage clusters for analytics, test and development applications, etc. and eliminates unnecessary copies of data.

Abstract: Systems and methods for replicating a snapshot of a volume are described. In one embodiment, a storage controller of a storage system may be operable to initialize a first replication process between a first storage volume of the first storage system and a second storage volume of a second storage system, copy content from a first system snapshot of the first storage volume to a second system snapshot of the first storage volume, and copy content from a first user snapshot of the first storage volume to the first system snapshot of the first storage volume. In some cases, a system snapshot is not accessible to a user and a user snapshot is accessible to the user. In some cases, at least one of the system snapshot and the user snapshot include a point in time capture of data on the first storage volume.

Abstract: Managing lowest point of coherency (LPC) memory using a service layer adapter, the adapter coupled to a processor and an accelerator on a host computing system, the processor configured for symmetric multi-processing, including receiving, by the adapter, a memory access instruction from the accelerator; retrieving, by the adapter, a real address for the memory access instruction; determining, using base address registers on the adapter, that the real address targets the LPC memory, wherein the base address registers direct memory access requests between the LPC memory and other memory locations on the host computing system; and sending, by the adapter, the memory access instruction and the real address to a media controller for the LPC memory, wherein the media controller for the LPC memory is attached to the adapter via a memory interface.