Patents Examined by Priya Rampersaud
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Patent number: 10170553Abstract: Device structure and fabrication methods for a bipolar junction transistor. An emitter layer is formed on a base layer and etched to form an emitter of the device structure. The emitter layer has a concentration of an element that varies as a function of the thickness of the emitter layer. The etch rate of the emitter layer varies as a function of the concentration of the element such that the emitter has a variable width over the thickness of the emitter layer.Type: GrantFiled: June 19, 2017Date of Patent: January 1, 2019Assignee: GLOBALFOUNDRIES Inc.Inventors: Renata Camillo-Castillo, Qizhi Liu, John J. Pekarik
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Patent number: 10163975Abstract: A light emitting apparatus is disclosed. The light emitting apparatus includes a light-transmissive substrate having a top surface and a bottom surface, at least one semiconductor light emitting device disposed on the top surface of the light-transmissive substrate, a reflective part disposed over the semiconductor light emitting device to reflect light from the semiconductor light emitting device toward the light-transmissive substrate, and a first wavelength converter disposed between the light-transmissive substrate and the reflective part.Type: GrantFiled: February 6, 2017Date of Patent: December 25, 2018Assignee: Seoul Semiconductor Co., Ltd.Inventor: Hyuck Jung Choi
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Patent number: 10153315Abstract: A photosensitive imaging apparatus and a method of forming such an apparatus are disclosed. The apparatus includes: a first semiconductor substrate, including a photosensitive semiconductor layer including an array of photodetectors; and a second semiconductor substrate, stacked with the first semiconductor substrate and including a pixel-circuitry semiconductor layer including an array of in-pixel amplifier circuitries. Each in-pixel amplifier circuitry includes at least one first pixel MOS transistor. Each first pixel MOS transistor has an active region disposed between the gate layer thereof and the first semiconductor substrate. The photosensitive imaging apparatus allows an effective reduction in noises produced during light reception of the in-pixel amplifier circuitries and an increased light utilization of the photodetectors.Type: GrantFiled: April 22, 2016Date of Patent: December 11, 2018Assignee: SHANGHAI JADIC OPTOELECTRONICS TECHNOLOGY CO., LTD.Inventors: Jianhong Mao, Cheng Xu
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Patent number: 10134840Abstract: Embodiments are directed to a method of fabricating a portion of a nanowire field effect transistor (FET). The method includes forming a sacrificial layer and a nanowire layer, removing a sidewall portion of the sacrificial layer and forming a diffusion block in a space that was occupied by the removed sidewall portion of the sacrificial layer. The method further includes forming a source region and a drain region such that the diffusion block is between the sacrificial layer and at least one of the source region and the drain region, and removing the sacrificial layer using a sacrificial layer removal process, wherein the diffusion block prevents the sacrificial layer removal process from also removing portions of at least one of the source region and the drain region.Type: GrantFiled: June 15, 2015Date of Patent: November 20, 2018Assignees: INTERNATIONAL BUSINESS MACHINES CORPORATION, GLOBALFOUNDRIES INC., STMICROELECTRONICS, INC.Inventors: Chun-Chen Yeh, Xiuyu Cai, Qing Liu, Ruilong Xie
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Patent number: 10068905Abstract: A device comprises a first inverter comprising a first p-type transistor (PU) and a first n-type transistor (PD), a second inverter cross-coupled to the first inverter comprising a second PU and a second PD, a first pass-gate transistor coupled between the first inverter and a first bit line and a second pass-gate transistor coupled between the second inverter and a second bit line, wherein at least one transistor has a two-stage fin structure, and wherein a width of a bottom portion of the two-stage fin structure is greater than a width of an upper portion of the two-stage fin structure.Type: GrantFiled: June 9, 2016Date of Patent: September 4, 2018Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventor: Jhon-Jhy Liaw
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Patent number: 10056450Abstract: A semiconductor device includes a semiconductor substrate with: a drift layer; a base layer; and a collector layer and a cathode layer. In the semiconductor substrate, when a region operating as an IGBT device is an IGBT region and a region operating as a diode device is a diode region, the IGBT and diode regions are arranged alternately in a repetitive manner; a damaged region is arranged on a surface portion of the diode region in the semiconductor substrate. The IGBT and diode regions are demarcated by a boundary between the collector and cathode layers; and a surface portion of the IGBT region includes: a portion having the damaged region at a boundary side with the diode region; and another portion without the damaged region arranged closer to an inner periphery side relative to the boundary side.Type: GrantFiled: January 29, 2015Date of Patent: August 21, 2018Assignee: DENSO CORPORATIONInventor: Kenji Kouno
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Patent number: 9997532Abstract: A semiconductor device includes stacked structure, openings passing through stacked structure, semiconductor patterns formed over inner walls of the openings, liner layers formed in the openings over the semiconductor patterns, and gap-fill insulating layers formed over the liner layers to fill the openings, wherein each of the gap-fill insulating layers seals an upper portion of the opening and includes at least one air gap.Type: GrantFiled: June 4, 2015Date of Patent: June 12, 2018Assignee: SK Hynix Inc.Inventors: Min Sung Ko, Sung Soon Kim, Wan Sup Shin
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Patent number: 9978853Abstract: A method of fabricating a semiconductor device includes forming a gate strip including a dummy electrode and a TiN layer. The method includes removing a first portion of the dummy electrode to form a first opening over a P-active region and an isolation region. The method includes performing an oxygen-containing plasma treatment on a first portion of the TiN layer; and filling the first opening with a first metal material. The method includes removing a second portion of the dummy electrode to form a second opening over an N-active region and the isolation region. The method includes performing a nitrogen-containing plasma treatment on a second portion of the TiN layer; and filling the second opening with a second metal material. The second portion of the TiN layer connects to the first portion of the TiN layer over the isolation region.Type: GrantFiled: March 13, 2017Date of Patent: May 22, 2018Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Ming Zhu, Hui-Wen Lin, Harry Hak-Lay Chuang, Bao-Ru Young, Yuan-Sheng Huang, Ryan Chia-Jen Chen, Chao-Cheng Chen, Kuo-Cheng Ching, Ting-Hua Hsieh, Carlos H. Diaz
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Patent number: 9960278Abstract: To provide a highly reliable semiconductor device manufactured by giving stable electric characteristics to a semiconductor device including an oxide semiconductor. In a manufacturing process of a transistor, an oxide semiconductor layer, a source electrode layer, a drain electrode layer, a gate insulating film, a gate electrode layer, and an aluminum oxide film are formed in this order, and then heat treatment is performed on the oxide semiconductor layer and the aluminum oxide film, whereby an oxide semiconductor layer from which an impurity containing a hydrogen atom is removed and which includes a region containing oxygen more than the stoichiometric proportion is formed. In addition, when the aluminum oxide film is formed, entry and diffusion of water or hydrogen into the oxide semiconductor layer from the air due to heat treatment in a manufacturing process of a semiconductor device or an electronic appliance including the transistor can be prevented.Type: GrantFiled: April 2, 2012Date of Patent: May 1, 2018Inventors: Yuhei Sato, Keiji Sato, Toshinari Sasaki, Tetsunori Maruyama, Atsuo Isobe, Tsutomu Murakawa, Sachiaki Tezuka
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Patent number: 9923095Abstract: The present invention provides a non-planar FET and a method of manufacturing the same. The non-planar FET includes a substrate, a fin structure, a gate and a gate dielectric layer. The fin structure is disposed on the substrate. The fin structure includes a first portion adjacent to the substrate wherein the first portion shrinks towards a side of the substrate. The gate is disposed on the fin structure. The gate dielectric layer is disposed between the fin structure and the gate. The present invention further provides a method of manufacturing the non-planar FET.Type: GrantFiled: December 15, 2016Date of Patent: March 20, 2018Assignee: UNITED MICROELECTRONICS CORP.Inventors: Chin-Cheng Chien, Chun-Yuan Wu, Chih-Chien Liu, Chin-Fu Lin, Chia-Lin Hsu
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Patent number: 9904125Abstract: A display panel includes a substrate, a plurality of thin film transistors (TFTs), a plurality common electrodes, a plurality of common electrode lines, a plurality of coupling electrodes, and a plurality of pixel electrodes. Each of the TFTs comprises a gate, a source, a drain and a channel layer coupling the source to the drain. The gate, the common electrodes, and the common electrode lines are formed on a surface of the substrate and are separated from each other. Each of the coupling electrodes couples a corresponding common electrode to a corresponding common electrode line, and a space is defined between the corresponding common electrode and the corresponding common electrode line.Type: GrantFiled: June 25, 2015Date of Patent: February 27, 2018Assignee: Century Technology (Shenzhen) Corporation LimitedInventors: Ming-Tsung Wang, Chih-Chung Liu, Kuo-Chieh Chi, Jian-Xin Liu
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Patent number: 9881837Abstract: A fuse device and method for fabricating the fuse device is disclosed. An exemplary fuse device includes a first contact and a second contact coupled with a metal-semiconductor alloy layer, wherein the metal-semiconductor alloy layer extends continuously between the first contact and the second contact. The metal-semiconductor alloy layer is disposed over an epitaxial layer that is disposed over a fin structure of a substrate.Type: GrantFiled: March 3, 2015Date of Patent: January 30, 2018Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Min-Chang Liang, Shien-Yang Wu, Wei-Chang Kung
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Patent number: 9853128Abstract: Devices and methods of growing unmerged epitaxy for fin field-effect transistor (FinFet) devices are provided. One method includes, for instance: obtaining a wafer having at least one source, at least one drain, and at least one fin; etching to expose at least a portion of the at least one fin; forming at least one sacrificial gate structure; and forming a first layer of an epitaxial growth on the at least one fin. One device includes, for instance: a wafer having at least one source, at least one drain, and at least one fin; a first layer of an epitaxial growth on the at least one fin; at least one second layer of an epitaxial growth superimposing the first layer of an epitaxial growth; and a first contact region over the at least one source and a second contact region over the at least one drain.Type: GrantFiled: June 10, 2015Date of Patent: December 26, 2017Assignee: GLOBALFOUNDRIES INC.Inventors: Hui Zang, Bingwu Liu
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Patent number: 9837387Abstract: A light emitting apparatus is disclosed. The light emitting apparatus includes a light-transmissive substrate having a top surface and a bottom surface, at least one semiconductor light emitting device disposed on the top surface of the light-transmissive substrate, a reflective part disposed over the semiconductor light emitting device to reflect light from the semiconductor light emitting device toward the light-transmissive substrate, and a first wavelength converter disposed between the light-transmissive substrate and the reflective part.Type: GrantFiled: March 29, 2012Date of Patent: December 5, 2017Assignee: Seoul Semiconductor Co., Ltd.Inventor: Hyuck Jung Choi
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Patent number: 9825198Abstract: A method of producing a plurality of optoelectronic semiconductor chips includes a) providing a layer composite assembly having a principal plane which delimits the layer composite assembly in a vertical direction, and includes a semiconductor layer sequence having an active region that generates and/or detects radiation, wherein a plurality of recesses extending from the principal plane in a direction of the active region are formed in the layer composite assembly; b) forming a planarization layer on the principal plane such that the recesses are at least partly filled with material of the planarization layer; c) at least regionally removing material of the planarization layer to level the planarization layer; and d) completing the semiconductor chips, wherein for each semiconductor chip at least one semiconductor body emerges from the semiconductor layer sequence.Type: GrantFiled: November 12, 2012Date of Patent: November 21, 2017Assignee: OSRAM Opto Semiconductors GmbHInventors: Patrick Rode, Lutz Hoeppel, Norwin von Malm, Stefan Illek, Albrecht Kieslich, Siegfried Herrmann
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Patent number: 9761464Abstract: A power MOSFET includes a substrate, a dielectric layer, solder balls, first and second patterned-metal layers. The substrate includes an active surface, a back surface, a source region and a gate region on the active surface, and a drain region on the back surface. The first patterned-metal layer disposed on the active surface includes a source electrode, a gate electrode, a drain electrode and a connecting trace. The source and gate electrodes electrically connect the source and gate regions. The connecting trace located at an edge of the substrate electrically connects the drain electrode. The dielectric layer disposed on the active surface exposes the first patterned-metal layer. The second patterned-metal layer includes UBM layers covering the source, gate and drain electrodes and a connecting metal layer covering the connecting trace and extending to the edge to electrically connect the drain region. The solder balls are disposed on the UBM layers.Type: GrantFiled: June 2, 2015Date of Patent: September 12, 2017Assignee: Excelliance MOS CorporationInventor: Yi-Chi Chang
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Patent number: 9748522Abstract: The invention relates to an illumination system comprising a light emitting device and a beam shaping element for generating an angular distribution of the light emitted from the illumination system. The beam shaping element is configured for recycling at least a part of the light emitted from a light emitting surface of the light emitting device via reflection back towards the light emitting surface. The illumination system further comprises a diffuser arranged substantially parallel to the light emitting surface for diffusing at least part of the recycled light. The diffuser is constituted of a translucent diffuser and/or a diffusely reflective electrode layer of the light emitting device. Limiting the angular distribution by recycling light, using the beam shaping element for recycling light via reflection, reduces glare when the illumination system is used in general lighting applications.Type: GrantFiled: April 21, 2010Date of Patent: August 29, 2017Assignee: PHILIPS LIGHTING HOLDING B.V.Inventors: Coen Adrianus Verschuren, Ferry Zijp
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Patent number: 9735239Abstract: A system and method for a channel region is disclosed. An embodiment comprises a channel region with multiple bi-layers comprising alternating complementary materials such as layers of InAs and layers of GaSb. The alternating layers of complementary materials provide desirable band gap characteristics for the channel region as a whole that individual layers of material may not.Type: GrantFiled: April 11, 2012Date of Patent: August 15, 2017Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Gerben Doornbos, Krishna Kumar Bhuwalka, Matthias Passlack
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Patent number: 9728603Abstract: Device structures for a bipolar junction transistor and methods of fabricating a device structure for a bipolar junction transistor. A base layer comprised of a first semiconductor material is formed. An emitter layer comprised of a second semiconductor material is formed on the base layer. The emitter layer is patterned to form an emitter finger having a length and a width that changes along the length of the emitter finger.Type: GrantFiled: June 22, 2015Date of Patent: August 8, 2017Assignee: GLOBALFOUNDRIES Inc.Inventors: Hanyi Ding, Vibhor Jain, Alvin J. Joseph, Anthony K. Stamper
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Patent number: 9705048Abstract: A light-emitting device includes a light emitting element, a resin package defining a recessed portion serving as a mounting region of the light emitting element, gate marks each formed on an outer side surface of the resin package, and leads disposed on the bottom surface of the recessed portion and electrically connected to the light emitting element. The light emitting element is mounted on the lead. The gate marks include a first gate mark formed on a first outer side surface of the resin package and a second gate mark formed on an outer side surface which is different than the first outer side surface.Type: GrantFiled: October 8, 2010Date of Patent: July 11, 2017Assignee: NICHIA CORPORATIONInventor: Masaki Hayashi