Abstract: The high-voltage transistor device has a p-type semiconductor substrate that is furnished with a p-type epitaxial layer. A well and a body region are located in the epitaxial layer. A source region is arranged in the body region, and a drain region is arranged in the well. A channel region is located in the body region between the well and the source region. A gate electrode is arranged above the channel region. In the part of the semiconductor substrate and the epitaxial layer underneath the source region and the channel region, a deep body region is present, which has a higher dopant concentration in comparison to the remainder of the semiconductor substrate.

Abstract: A semiconductor structure including a semiconductor wafer. The semiconductor wafer includes a gate structure, a first trench in the semiconductor wafer adjacent to a first side of the gate structure and a second trench adjacent to a second side of the gate structure, the first and second trenches filled with a doped epitaxial silicon to form a source in the filled first trench and a drain in the filled second trench such that each of the source and drain are recessed and have an inverted facet. In a preferred exemplary embodiment, the epitaxial silicon is doped with boron.

Abstract: There is provided a power semiconductor device including: a first semiconductor region of a first conductivity type; second semiconductor regions formed in the first semiconductor region and being of a second conductivity type; a well region formed above the second semiconductor regions and being of the second conductivity type; and a source region formed in the well region and being of the first conductivity type, wherein the second semiconductor regions include 1 to n layers formed from a lower portion of the device extending a in a direction of height of the device, and in the case that the widest width of the of the second semiconductor region of the nth layer is Pn, P1<Pn (n?2).

Abstract: The invention relates to integrated circuit fabrication, and more particularly to a metal gate structure. An exemplary structure for a CMOS semiconductor device comprises a substrate comprising an isolation region surrounding and separating a P-active region and an N-active region; a P-metal gate electrode over the P-active region and extending over the isolation region, wherein the P-metal gate electrode comprises a P-work function metal and an oxygen-containing TiN layer between the P-work function metal and substrate; and an N-metal gate electrode over the N-active region and extending over the isolation region, wherein the N-metal gate electrode comprises an N-work function metal and a nitrogen-rich TiN layer between the N-work function metal and substrate, wherein the nitrogen-rich TiN layer connects to the oxygen-containing TiN layer over the isolation region.

Abstract: A method of forming a metal chalcogenide material. The method comprises exposing a metal to a solution comprising a chalcogenide element source compound and an acid. Methods of forming memory cells including the metal chalcogenide material are also disclosed.

Abstract: A light emitting device according to the embodiment includes a support substrate; a first light emitting structure disposed on the support substrate and including a first conductive type first semiconductor layer, a first active layer, and a second conductive type second semiconductor layer; a first reflective electrode under the first light emitting structure; a first metal layer around the first reflective electrode; a second light emitting structure disposed on the support substrate and including a first conductive type third semiconductor layer, a second active layer, and a second conductive type fourth semiconductor layer; a second reflective electrode under the second light emitting structure; a second metal layer around the second reflective electrode; and a contact part making contact with an inner portion of the first conductive type first semiconductor layer of the first light emitting structure and electrically connected to the second reflective electrode.

Abstract: A light emitting device according to the embodiment includes a first light emitting structure including a first conductive type first semiconductor layer, a first active layer under the first conductive type first semiconductor layer, and a second conductive type second semiconductor layer under the first active layer; a first reflective electrode under the first light emitting structure; a second light emitting structure including a first conductive type third semiconductor layer, a second active layer under the first conductive type third semiconductor layer, and a second conductive type fourth semiconductor layer under the second active layer; a second reflective electrode under the second light emitting structure; a contact part that electrically connects the first conductive type first semiconductor layer of the first light emitting structure to the second reflective electrode; and a first insulating ion implantation layer between the contact part and the second conductive type second semiconductor layer

Abstract: The present invention provides a non-planar FET which includes a substrate, a fin structure, a gate and a gate dielectric layer. The fin structure is disposed on the substrate. The fin structure includes a first portion adjacent to the substrate wherein the first portion shrinks towards a side of the substrate. The gate is disposed on the fin structure. The gate dielectric layer is disposed between the fin structure and the gate. The present invention further provides a method of manufacturing the non-planar FET.

Abstract: A semiconductor light emitting device and method of manufacturing the semiconductor light emitting device are provided. The semiconductor light emitting device includes a light emitting structure including a first conductivity type semiconductor layer, an active layer, and a second conductivity type semiconductor layer. The device may also includes a first electrode connected to the first conductivity type semiconductor layer, and a second electrode connected to the second conductivity type semiconductor layer and having a pad region and a finger region extended from the pad region in one direction.

Abstract: A conductive contact pattern is formed on a surface of solar cell by forming a thin conductive layer over at least one lower layer of the solar cell, and ablating a majority of the thin conductive layer using a laser beam, thereby leaving behind the conductive contact pattern. The laser has a top-hat profile, enabling precision while scanning and ablating the thin layer across the surface. Heterocontact patterns are also similarly formed.

Abstract: A method of fabricating a graphene oxide material in which oxidation is confined within the graphene layer and that possesses a desired band gap is provided. The method allows specific band gap values to be developed. Additionally, the use of masks is consistent with the method, so intricate configurations can be achieved. The resulting graphene oxide material is thus completely customizable and can be adapted to a plethora of useful engineering applications.

Abstract: A chip package structure includes a carrier and a chip group. The chip group includes a pair of first chips that are identical IC chips. The pair of first chips are disposed on the carrier in opposite directions and parallel to each other, and electrically connected with the carrier.

Abstract: A spin transport device includes a semiconductor layer 3, a first ferromagnetic layer 1 provided on the semiconductor layer 3 via a first tunnel barrier layer 5A, and a second ferromagnetic layer 2 provided on the semiconductor layer 3 via a second tunnel barrier layer 5B to be spaced from the first ferromagnetic layer 1, and the semiconductor layer 3 includes a first region RI broadening in a direction away from the first ferromagnetic layer 1 along a direction orthogonal to a thickness direction from the first ferromagnetic layer 1, and a second region R12 extending in a direction toward the second ferromagnetic layer 2 along the direction orthogonal to the thickness direction from the first ferromagnetic layer 1. The second region R12 has a relatively higher impurity concentration than the first region R1.

Abstract: A FinFET comprises an isolation region formed in a substrate, a reverse T-shaped fin formed in the substrate, wherein a bottom portion of the reverse T-shaped fin is enclosed by the isolation region and an upper portion of the reverse T-shaped fin protrudes above a top surface of the isolation region. The FinFET further comprises a gate electrode wrapping the reverse T-shaped fin.

Abstract: An IC package is provided. The IC package comprises a leadframe comprising a metal strip (222) partially etched on a first side. The leadframe may be configured for an IC chip to be mounted thereon and for a plurality of bonding areas (218) to be electrically coupled to the leadframe and the IC chip. The IC chip, the bonding areas, and a portion of the metal leadframe are covered with an encapsulation compound, with a plurality of contact pads (206) protruding from the bottom surface of the leadframe. The bottom surface of the leadframe may be etched one or more times during the manufacturing process to reduce the depth of the undercutting. A method for manufacturing an IC package is also provided.

Abstract: Semiconductor-on-oxide structures and related methods of forming such structures are disclosed. In one case, a method includes: forming a first dielectric layer over a substrate; forming a first conductive layer over the first dielectric layer, the first conductive layer including one of a metal or a silicide; forming a second dielectric layer over the first conductive layer; bonding a donor wafer to the second dielectric layer, the donor wafer including a donor dielectric and a semiconductor layer; cleaving the donor wafer to remove a portion of the donor semiconductor layer; forming at least one semiconductor isolation region from an unremoved portion of the donor semiconductor layer; and forming a contact to the first conductive layer through donor dielectric and the second dielectric layer.

Abstract: A display device according to an exemplary embodiment of the present invention includes a display portion including a plurality of display pixels displaying an image and a dummy portion including a plurality of dummy pixels formed in a periphery region of the display portion. An electrostatic test element group (TEG) may be formed in at least one of the dummy pixels.

Abstract: The present invention relates generally to power switches for aircraft. According to a first aspect, the present invention provides an integrated solid state power switch for fault protection in an aircraft power distribution system. The integrated solid state power switch is formed of semiconductor material that provides a field effect transistor (FET) channel that is operable during normal device operation to provide an operating current flow path and a bipolar transistor channel that is operable during device overload conditions to provide an overload current flow path. A method for manufacturing such an integrated solid state power switch is also described. Various embodiments of the invention provide automatic overload current protection for aircraft systems without the need to use bulky switches or heavy cooling equipment.

Abstract: A semiconductor device having a substrate, and at least one contact, situated on and/or above a surface of the substrate, having at least one layer made of a conductive material, the conductive material including at least one metal. The layer made of the conductive material is sputtered on, and has tear-off marks on at least one outer side area between an outer base area facing the surface and an outer contact area facing away from the surface. A manufacturing method for a semiconductor device having at least one contact is also described.

Abstract: Exemplary embodiments of the present invention relate to light emitting diodes including a plurality of light emitting cells on a substrate to be suitable for AC driving. The light emitting diode includes a substrate and a plurality of light emitting cell formed on the substrate. Each light emitting cell includes a first region at a boundary of the light emitting cell and a second region opposite to the first region. A first electrode pad is formed in the first region of the light emitting cell. A second electrode pad having a linear shape is disposed to face the first electrode pad while regionally defining a peripheral region together with the boundary of the second region. A wire connects the first electrode pad to the second electrode pad between two adjacent light emitting cells.