Patents Examined by Quan Tra
  • Patent number: 12034440
    Abstract: Systems, apparatuses, and methods for implementing a combo scheme for direct current (DC) level shifting of signals are disclosed. A receiver circuit receives an input signal on a first interface. The first interface is coupled to a resistor in parallel with a capacitor which passes the input signal to a second interface. Also, the first interface is coupled to a first pair of current sources between ground and a voltage source, and the second interface is coupled to a second pair of current sources between ground and the voltage source. An op-amp drives the current sources based on a difference between a sensed common mode voltage and a reference voltage. Based on this circuit configuration, the receiver circuit is able to prevent baseline wander, perform a DC level shift of the input signal, and achieve linear equalization of the input signal.
    Type: Grant
    Filed: December 30, 2021
    Date of Patent: July 9, 2024
    Assignee: Advanced Micro Devices, Inc.
    Inventors: Rajesh Kumar, Edoardo Prete, Gerald R. Talbot, Ethan Crain, Tracy J. Feist, Jeffrey Cooper
  • Patent number: 12034406
    Abstract: Radio frequency (RF) mixer circuits having a complementary frequency multiplier module that requires no balun to multiply a lower frequency base oscillator signal to a higher frequency local oscillator (LO) signal, and which has a significantly reduced IC area compared to balun-based frequency multipliers. In one embodiment, the complementary frequency multiplier module includes a complementary pair of FETs controlled by an applied base oscillator signal. The complementary FETs are coupled to a common-gate FET amplifier and alternate becoming conductive in response to the base oscillator signal. The alternating switching of the complementary FETs in response to the opposing phases of the base oscillator signal cause the common-gate FET amplifier to output a higher frequency local oscillator (LO) signal. The LO signal is coupled to the LO input of a mixer or mixer core of a type suitable for use in conjunction with a frequency multiplier.
    Type: Grant
    Filed: March 3, 2023
    Date of Patent: July 9, 2024
    Assignee: Murata Manufacturing Co., Ltd.
    Inventor: John Birkbeck
  • Patent number: 12028077
    Abstract: A phase detector circuit for use with a multi-level signaling communication protocol on a serial communication link is disclosed. The phase detector circuit employs multiple phase and logic circuits to detect data state changes between adjacent ones of voltage levels corresponding to different data states in the communication protocol, and generates early/late signals using the detected data state changes. The phase detector circuit statistically filters data state transitions between non-adjacent voltage levels to improve phase locking and reduce recovered clock jitter.
    Type: Grant
    Filed: February 22, 2023
    Date of Patent: July 2, 2024
    Assignee: Apple Inc.
    Inventors: Wenbo Liu, Gokce Gurun, Ajay M. Rao, Sanjeev K. Maheshwari
  • Patent number: 12028057
    Abstract: A system includes a receiver. The receiver includes an input stage having an input and an output, and a first resistor coupled between the output of the input stage and the input of the input stage. The receiver also includes an output stage having an input and an output, wherein the input of the output stage is coupled to the output of the input stage, and a feedback path coupled between the output of the output stage and the input of the input stage, the feedback path including a second resistor.
    Type: Grant
    Filed: September 23, 2022
    Date of Patent: July 2, 2024
    Assignee: QUALCOMM INCORPORATED
    Inventor: Masoud Roham
  • Patent number: 12022747
    Abstract: Embodiments disclosed herein include a resonator for use in quantum computing. The resonator can include a housing that is disposed along a resonator axis. The housing can have a first portion extending from a housing distal end to near a qubit location and a second portion extending from near the qubit location to a housing proximal end. The housing can define a cavity extending from a cavity proximal end to a cavity distal end along a portion of the resonator axis. The housing can include a protrusion extending axially from the housing distal end along the resonator axis to near the qubit location. A proximal portion of the protrusion can include a tapered portion. The resonator can include a qubit extending into the cavity at the qubit location.
    Type: Grant
    Filed: April 22, 2020
    Date of Patent: June 25, 2024
    Assignee: RadiaBeam Technologies, LLC
    Inventors: Sergey Kutsaev, Ronald Agustsson, Kirill Taletski
  • Patent number: 12009951
    Abstract: Embodiments address optimization of an electrical interface between an optical host device and an optical module device at installation time. Certain methods try each entry in a set of Finite Impulse Response (FIR) filter settings at the host transmitter, while asking the module to measure the signal integrity for each. The module will then provide an indication of which entry was the best choice for signal integrity in the current hardware configuration. Note that for the module to host electrical interface, this same technique can be used in reverse, whereby the host asks the module to configure its transmitting FIR filter, and the host records and keeps track of which filter setting is the best, and then configures the module with that filter setting. In both cases, for modules supporting CMIS (Common Management Interface Specification) for module configuration and control, methods are provided.
    Type: Grant
    Filed: February 26, 2021
    Date of Patent: June 11, 2024
    Assignee: Marvell Asia Pte Ltd.
    Inventors: Todd Rope, Ilya Lyubomirsky, Whay Sing Lee, Arash Farhoodfar
  • Patent number: 12005814
    Abstract: The power supply device 10 including: a power transmission unit 40 that is provided on the floor part F and that extends along a slide direction in which the seat S slides; and a power receiving unit 70 that is provided to the seat S and that receives power from the power transmission unit 40 in a contactless fashion. The power transmission unit 40 is provided so that the length dimension thereof in the slide direction is longer than the length dimension thereof in a direction that is orthogonal to the slide direction, and a part of the power receiving unit 70 that receives power from the power transmission unit 40 is positioned close to the power transmission unit 40 within an installation area of the power transmission unit 40 while the seat S slides and rotates.
    Type: Grant
    Filed: February 17, 2020
    Date of Patent: June 11, 2024
    Assignees: AUTONETWORKS TECHNOLOGIES, LTD., SUMITOMO WIRING SYSTEMS, LTD., SUMITOMO ELECTRIC INDUSTRIES, LTD.
    Inventors: Yasuyuki Yamamoto, Hidetoshi Ishida, Satoshi Yamamoto, Kenichi Sagara, Keizo Watanabe, Yutaka Kikuchi, Shu Sasaki, Fumihiro Sato
  • Patent number: 11996856
    Abstract: The present disclosure provides a circuitry. The circuitry includes a comparator and a signal correlated circuit. The comparator includes a first input terminal, a second input terminal, and an output terminal. The signal correlated circuit includes a first input terminal, a second input terminal, a first output terminal, and a second output terminal. The first input terminal is coupled to receive a first input signal. The second input terminal is coupled to receive a second input signal independent from the first input signal. The first output terminal is configured to generate a first output signal and to send the first output signal to the first input terminal of the comparator. The second output terminal is configured to generate a second output signal and to send the second output signal to the second input terminal of the comparator. The first output signal and the second output signal are correlated.
    Type: Grant
    Filed: December 14, 2022
    Date of Patent: May 28, 2024
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.
    Inventors: Chung-Ting Lu, Chih-Chiang Chang, Chung-Chieh Yang
  • Patent number: 11990885
    Abstract: A method for manufacturing an acoustic device includes providing a substrate, providing a bottom electrode over the substrate, providing a sacrificial layer on the bottom electrode, patterning the bottom electrode and the sacrificial layer, polishing the sacrificial layer such that a portion of the sacrificial layer remains on the bottom electrode, and removing the remaining portion of the sacrificial layer via a cleaning process such that a surface roughness of the bottom electrode is maintained. By performing the polishing such that a portion of the sacrificial layer remains on the bottom electrode and subsequently removing that portion of the sacrificial layer via a cleaning process that maintains the surface roughness of the bottom electrode, the subsequent growth of a piezoelectric layer on the bottom electrode can be substantially improved.
    Type: Grant
    Filed: June 29, 2021
    Date of Patent: May 21, 2024
    Assignee: Qorvo US, Inc.
    Inventors: Buu Quoc Diep, Derya Deniz, Matthew L. Wasilik, John Belsick
  • Patent number: 11990770
    Abstract: Systems, methods, and apparatuses for receiving wireless power using a wireless power receiver client architecture are disclosed. A simplified wireless power receiver apparatus includes an energy storage device and a radio frequency (RF) transceiver including an antenna. Energy harvester circuitry is coupled to the energy storage device and the RF transceiver, and control circuitry is coupled to the energy storage device, the RF transceiver, and the energy harvester. The control circuitry causes the RF transceiver to: establish a connection with a wireless power transmitter (WPT), transmit a beacon signal to the WPT, and receive a wireless power signal from the WPT. The control circuitry causes the energy harvester to deliver at least a portion of energy of the wireless power signal to the energy storage device for storage therein. In some embodiments, a single antenna is utilized both for transmitting the beacon signal and for receiving the wireless power signal.
    Type: Grant
    Filed: November 3, 2022
    Date of Patent: May 21, 2024
    Assignee: Ossia Inc.
    Inventors: Hatem Ibrahim Zeine, Douglas Wayne Williams, James J. Wojcik
  • Patent number: 11983025
    Abstract: An electric device includes: a first power domain; a second power domain; a third power domain, where during power-up, the third, the second, and the first power domains are configured to be powered up sequentially, where during standby-exit, the first, the second, and the third power domains are configured to be powered up sequentially; isolation paths that provide controlled signal transmission among the first, the second, and the third power domains, where each isolation path includes an isolation circuit between an input power domain and an output power domain of the isolation path; and a control circuit in the first power domain, where for each isolation path, the control circuit is configured to generate an isolation control signal for the isolation circuit, where the isolation circuit is configured enable or disable signal transmission along the isolation path.
    Type: Grant
    Filed: October 17, 2022
    Date of Patent: May 14, 2024
    Assignee: STMICROELECTRONICS INTERNATIONAL N.V.
    Inventors: Venkata Narayanan Srinivasan, Mayankkumar Hareshbhai Niranjani, Dhulipalla Phaneendra Kumar, Gourav Garg, Sourabh Banzal
  • Patent number: 11962440
    Abstract: In certain aspects, a comparator includes an input stage and a regeneration stage. The input stage includes a first input circuit coupled to a first node and a second node, a first switching transistor configured to enable the first input circuit if a previous bit value is one, a second input circuit coupled to the first node and the second node, and a second switching transistor configured to enable the second input circuit if the previous bit value is zero. The regeneration stage includes a first inverter, a second inverter cross coupled with the first inverter, a first drive transistor coupled to the first inverter, wherein a gate of the first drive transistor is coupled to the second node, and a second drive transistor coupled to the second inverter, wherein a gate of the second drive transistor is coupled to the first node.
    Type: Grant
    Filed: December 14, 2021
    Date of Patent: April 16, 2024
    Assignee: QUALCOMM INCORPORATED
    Inventors: Darius Valaee, Patrick Isakanian
  • Patent number: 11962307
    Abstract: An output circuit includes a comparator circuit, a voltage conversion circuit and a signal output circuit. The comparator circuit detects an operating mode based on a first supply voltage and a second supply voltage and generates a first control signal. The voltage conversion circuit adjusts a level of an output voltage from a low-dropout regulator according to the first control signal to generate a first voltage, and generates a second voltage according to the first control signal and the first voltage. The signal output circuit adjusts a level of a digital signal according to the first voltage, the second voltage and the first supply voltage to generate a digital output signal corresponding to the operating mode.
    Type: Grant
    Filed: December 23, 2022
    Date of Patent: April 16, 2024
    Assignee: SIGMASTAR TECHNOLOGY LTD.
    Inventors: Hao Wang, Zhen-Yang Pang
  • Patent number: 11955986
    Abstract: A comparator circuit, including an input circuit, first and second inverting amplification circuits, first and second coupling circuits, and a feedback circuit, wherein the input circuit generates an amplified input signal based on positive and negative input voltages, the first inverting amplification circuit generates an intermediate amplified signal based on the amplified input signal during a sampling period, the second inverting amplification circuit generates a comparison result signal based on the intermediate amplified signal during the sampling period, the first coupling circuit is connected between the input circuit and the first inverting amplification circuit, the second coupling circuit is connected between the first inverting amplification circuit and the second inverting amplification circuit, and the feedback circuit amplifies the input node of the first inverting amplification circuit with a rail-to-rail voltage corresponding to a power supply voltage or a ground voltage based on the comparis
    Type: Grant
    Filed: January 13, 2023
    Date of Patent: April 9, 2024
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventor: Hyochang Kim
  • Patent number: 11942861
    Abstract: Devices and methods for operating a charge pump. In some implementations, a charge pump module includes a clock circuit configured generate to a first clock signal and a second clock signal, the first clock signal having a lower frequency than the second clock signal. The charge pump module also includes a driving circuit configured to generate a first set of clock signals based on the first clock signal and a second set of clock signals based on the second clock signal, the driving circuit coupled to the clock circuit. The charge pump module further includes a charge pump core including a set of capacitances, the charge pump core configured to charge the set of capacitances based the first set of clock signals and the second set of clock signals.
    Type: Grant
    Filed: December 20, 2022
    Date of Patent: March 26, 2024
    Assignee: Skyworks Solutions, Inc.
    Inventors: Bo Zhou, Guillaume Alexandre Blin
  • Patent number: 11942795
    Abstract: A multi-antenna system for harvesting energy and transmitting data includes an energy storing unit, antenna transmission units, and a load unit. Each antenna transmission unit includes an antenna module, a splitting module, an energy generation module, and a data processing module. The splitting module splits a wireless signal received by the antenna module into a first splitting signal and a second splitting signal and transmits the first splitting signal to an energy generation module to convert the first splitting signal into electrical energy stored in an energy storing unit and provided to the data processing module. The energy storing unit provides the electrical energy for the load unit. The data processing module receives one of the second splitting signals, converts it into a control signal, and transmits the control signal to the load unit. The load unit operates according to the control signal.
    Type: Grant
    Filed: November 28, 2022
    Date of Patent: March 26, 2024
    Assignee: Netronix, Inc.
    Inventors: Fang Ming Tsai, You Wei Zhang, Jun Sheng Lin
  • Patent number: 11936352
    Abstract: Embodiments relate to an amplifier circuit. The amplifier circuit includes multiple transistors. Each transistor is configured to receive an input signal and output an amplified signal. The amplifier circuit additionally includes a set of input chopper circuits and a set of output chopper circuits. Each output chopper circuit corresponds to one input chopper of the set of input choppers. Each input chopper circuit and its corresponding output chopper are controlled by one or more control signals from a set of control signals. Each input chopper circuit is configured to selectively connect each transistor of a transistor pair to a first input terminal or a second input terminal based on a value of the one or more control signals. Moreover, each output chopper circuit is configured to selectively connect each transistor of the transistor pair to a first output terminal or a second output terminal based on the value of the one or more control signals.
    Type: Grant
    Filed: January 21, 2021
    Date of Patent: March 19, 2024
    Assignee: APPLE INC.
    Inventors: Erhan Ozalevli, Evaldo M. Miranda, Jr.
  • Patent number: 11929728
    Abstract: A packaged acoustic wave filter component can include an acoustic wave device including a first piezoelectric layer and an interdigital transducer electrode on the first piezoelectric layer. A support layer may be included over the acoustic wave device, and the packaged hybrid filter component can also include a bulk acoustic wave resonator over the support layer. A cap layer may extend over and encapsulate the bulk acoustic wave resonator. One or more external vias may extend through the support layer and the underlying layers of the acoustic wave device to provide electrical communication with the packaged bulk acoustic wave generator.
    Type: Grant
    Filed: November 18, 2020
    Date of Patent: March 12, 2024
    Assignee: Skyworks Solutions, Inc.
    Inventors: Keiichi Maki, Hironori Fukuhara, Rei Goto
  • Patent number: 11923822
    Abstract: An acoustic wave filter component can include a surface acoustic wave device including a first piezoelectric layer, an interdigital transducer electrode on the first piezoelectric layer, and an additional layer, such as a temperature compensation layer, over the interdigital transducer electrode. The acoustic wave filter component can also include a bulk acoustic wave resonator supported by the additional layer. The additional layer may be a layer on which a surface acoustic wave of the surface acoustic wave device will propagate. The bulk acoustic wave resonator may include an air cavity, where a shape of the air cavity is defined in part by the additional layer.
    Type: Grant
    Filed: November 18, 2020
    Date of Patent: March 5, 2024
    Assignee: Skyworks Solutions, Inc.
    Inventors: Keiichi Maki, Hironori Fukuhara, Rei Goto
  • Patent number: 11899049
    Abstract: The present invention discloses a comparison circuit having adaptive comparison mechanism is provided. A comparator is enabled by an enabling signal having an enabling state during a comparison stage to compare a first voltage and a second voltage to generate a comparison result. A comparison determining circuit sets a stage indication signal at an unfinished state and a finished state before and after the comparison result is generated. A time accumulating circuit starts to accumulate an accumulated time when the enabling signal is at the enabling state and stops accumulating when the stage indication signal is at the finished state to generate a comparison time. A determining circuit performs statistics on the comparison time to generate a predetermined threshold time and sets a predetermined comparison result as the comparison result under the condition that the comparison result is not generated and the accumulated time exceeds the predetermined threshold time.
    Type: Grant
    Filed: October 25, 2022
    Date of Patent: February 13, 2024
    Assignee: REALTEK SEMICONDUCTOR CORPORATION
    Inventor: Shih-Hsiung Huang