Patents Examined by Quan Tra
  • Patent number: 10923958
    Abstract: The present disclosure relates to a power transmitter, a resonance-type contactless power supply and a control method. The inverter circuit is controlled to provide a high-frequency AC current with a voltage strength parameter so that a current strength parameter (e.g., a peak value or an effective value of the current) of the AC current flowing through a transmitting coil and that through a receiving coil have a predetermined relationship. Thus, an equivalent load impedance is adjusted so that the system efficiency is optimized.
    Type: Grant
    Filed: May 6, 2019
    Date of Patent: February 16, 2021
    Assignee: Silergy Semiconductor Technology (Hangzhou) LTD
    Inventors: Wang Zhang, Feng Yu
  • Patent number: 10923952
    Abstract: In one embodiment, a power converter includes a wireless transmitter coil and a resonant capacitor that is configured to resonate at a first frequency. The wireless transmitter coil and resonant capacitor are configured to receive an alternating current at a second frequency such that the power converter outputs a first voltage that is dependent on the second frequency. In one embodiment, the first and second frequency are substantially equal. The power converter may also include an interconnection link configured to substantially double or vary the first voltage depending on a duty cycle that is applied to the interconnection link.
    Type: Grant
    Filed: March 28, 2016
    Date of Patent: February 16, 2021
    Assignee: CHARGEDGE, INC.
    Inventor: Sanjaya Maniktala
  • Patent number: 10924094
    Abstract: A pulse width modulation control circuit and a control method of a pulse width modulation signal are provided. A counter circuit generates a count value according to a phase-locked loop clock, and resets the count value according to a transition point of a synchronization signal. A comparison circuit compares the count value with a duty ratio set value, and sets the pulse width modulation signal to a high level while the count value is less than the duty ratio set value.
    Type: Grant
    Filed: September 3, 2019
    Date of Patent: February 16, 2021
    Assignee: Power Forest Technology Corporation
    Inventor: Yueh-Chang Chen
  • Patent number: 10911026
    Abstract: A capacitor circuit includes a first terminal, a first to a third transistor and a first capacitor. The first transistor includes a first terminal configured to be coupled to a first current source and the first terminal of the capacitor circuit, and a second terminal coupled to a reference voltage terminal. The second transistor includes a first terminal configured to be coupled to a second current source, a second terminal coupled to the reference voltage terminal, and a control terminal coupled to the first terminal of the second transistor and a control terminal of the first transistor. The third transistor includes a first terminal configured to be coupled to a third current source and the first terminal of the first transistor, a second terminal coupled to the reference voltage terminal, and a control terminal coupled to the control terminal of the second transistor.
    Type: Grant
    Filed: September 24, 2019
    Date of Patent: February 2, 2021
    Assignee: RichWave Technology Corp.
    Inventor: Ting-Yuan Cheng
  • Patent number: 10910881
    Abstract: According to one embodiment, an electronic apparatus includes a signal detector and processor circuitry. The signal detector is configured to detect communication information based on a wireless signal. The processor circuitry is configured to determine at least one of (1) a first period to wait from a timing of when power transmission is ended to a timing of when power transmission is started, (2) a second period to wait from a timing of when the wireless signal is not detected to a timing of when power transmission is started, and (3) a third period for continuously performing power transmission. The processor circuitry is configured to transmit a power with electromagnetic wave according to at least one of the first period, the second period, and the third period.
    Type: Grant
    Filed: March 11, 2019
    Date of Patent: February 2, 2021
    Assignee: KABUSHIKI KAISHA TOSHIBA
    Inventors: Kentaro Taniguchi, Tomoko Adachi
  • Patent number: 10886911
    Abstract: A positive-logic FET switch stack that does not require a negative bias voltage, exhibits high isolation and low insertion/mismatch loss, and may withstand high RF voltages. Embodiments include a FET stack comprising series-coupled positive-logic FETs (i.e., FETs not requiring a negative voltage supply to turn OFF), series-coupled on at least one end by an “end-cap” FET of a type that turns OFF when its VGS is zero volts. The one or more end-cap FETs provide a selectable capacitive DC blocking function or a resistive signal path. Embodiments include a stack of FETs of only the zero VGS type, or a mix of positive-logic and zero VGS type FETs with end-cap FETs of the zero VGS type. Some embodiments withstand high RF voltages by including combinations of series or parallel coupled resistor ladders for the FET gate resistors, drain-source resistors, body charge control resistors, and one or more AC coupling modules.
    Type: Grant
    Filed: March 28, 2018
    Date of Patent: January 5, 2021
    Assignee: pSemi Corporation
    Inventors: Simon Edward Willard, Tero Tapio Ranta, Matt Allison, Shashi Ketan Samal
  • Patent number: 10211811
    Abstract: The disclosure relates to a tunable filter. The tunable filter includes: a filter input; a filter output; at least one feedback loop coupled between the filter output and the filter input, where the at least one feedback loop includes at least one tunable feedback capacitance which is configured to tune a cut-off frequency of the tunable filter; and an active element, coupled between the filter input and the filter output and configured to drive the at least one tunable feedback capacitance, the active element having a transfer function with a primary pole and at least one secondary pole, where the active element includes a first stabilization element that is coupled to a first internal node of the active element.
    Type: Grant
    Filed: February 27, 2018
    Date of Patent: February 19, 2019
    Assignee: Huawei Technologies Co., Ltd.
    Inventor: Giuseppe Gramegna
  • Patent number: 10210946
    Abstract: According to some aspects, a low-leakage switch is provided. In some embodiments, the low-leakage switch includes a plurality of pass transistors in series that selectively couple two ports of the low-leakage switch and a node biasing circuit coupled to a node between the plurality of pass transistors. In these embodiments, the node biasing circuit may adjust a voltage at the node to change the gate-to-source voltage of the pass transistors and, thereby, reduce the leakage current through the pass transistors when the low-leakage switch is turned off. The node biasing circuit may also include circuitry to reduce the leakage current introduced by the node biasing circuit into the node when the low-leakage switch is turned on.
    Type: Grant
    Filed: October 28, 2016
    Date of Patent: February 19, 2019
    Assignee: Analog Devices, Inc.
    Inventor: Howard R. Samuels
  • Patent number: 10205300
    Abstract: Laser dazzler devices and methods of using laser dazzler devices are disclosed. More specifically, embodiments of the present invention provide laser dazzling devices power by one or more green laser diodes characterized by a wavelength of about 500 nm to 540 nm. In various embodiments, laser dazzling devices according to the present invention include non-polar and/or semi-polar green laser diodes. In a specific embodiment, a laser dazzling device includes a plurality of green laser diodes.
    Type: Grant
    Filed: December 30, 2015
    Date of Patent: February 12, 2019
    Inventors: James W. Raring, Paul Rudy, Vinod Khosla, Pierre Lamond, Steven P. Denbaars, Shuji Nakamura, Richard T. Ogawa
  • Patent number: 10199865
    Abstract: In accordance with some embodiments, a transmitter for wireless transfer includes a rectifier that receives an AC voltage and provides a DC voltage; a capacitor that receives and smooths the DC voltage; a regulator that receives the DC voltage and outputs an input voltage; and a wireless transmitter that receives the input voltage and transmits wireless power.
    Type: Grant
    Filed: April 16, 2015
    Date of Patent: February 5, 2019
    Assignee: Integrated Device Technology, Inc.
    Inventor: Mehmet K. Nalbant
  • Patent number: 10175660
    Abstract: According to one embodiment, a control device in a power electronics device includes a controller, a configuration determiner and a manager. The controller performs control associated with power conversion, in accordance with a first logical configuration of control between the power electronics device and other power electronics device. The configuration determiner performs determination processing of a second logical configuration when a change condition of the first logical configuration is satisfied. The manager instructs the controller to perform the control in accordance with the second logical configuration, the manager performing management such that the controller performs the control in accordance with previously given control information for a period after the change condition of the first logical configuration is satisfied and until the manager instructs the controller to perform the control associated with the power conversion in accordance with the second logical configuration.
    Type: Grant
    Filed: October 28, 2015
    Date of Patent: January 8, 2019
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Fumiaki Kanayama, Yusuke Doi, Yasuyuki Nishibayashi
  • Patent number: 10170981
    Abstract: A bi-directional charge pump cell includes a p-type substrate having a main surface. A first n-well is formed in the p-type substrate that includes n+ doped regions formed in the first n? well at the main surface. A first p-well is formed in the first n? well that includes p+ doped regions formed in the first p-well at the main surface. A second n-well is formed in the first p-well that includes n+ doped regions and PMOS transistors formed at the main surface. A second p-well is formed in the first n-well that includes p+ doped regions at the main surface. A third p-well is defined in the second p-well that includes p+ doped regions and NMOS transistors at the main surface.
    Type: Grant
    Filed: January 17, 2018
    Date of Patent: January 1, 2019
    Assignees: Akustica, Inc., Robert Bosch GmbH
    Inventors: Milap J. Dalal, Matthew A. Zeleznik
  • Patent number: 10164633
    Abstract: System and method for providing precision a self calibrating resistance circuit is described that provides for matching a reference resistor using dynamically configurable resistance networks. The resistor network is coupled to the connection, wherein the resistor network provides a configurable resistance across the connection. In addition, the resistor network comprises a digital resistor network and an analog resistor network. Also, the circuit includes control circuitry for configuring the configurable resistance based on a reference resistance of the reference resistor. The configurable resistance is configured by coarsely tuning the resistor network through the digital resistor network and fine tuning the resistor network through the analog resistor network.
    Type: Grant
    Filed: July 10, 2017
    Date of Patent: December 25, 2018
    Assignee: Invensas Corporation
    Inventors: Curtis Dicke, George Courville, David Edward Fisch, Randall Sandusky, Kent Stalnaker
  • Patent number: 10164472
    Abstract: Wireless charging of portable electronic devices is carried out by detecting load variations caused by the device and dynamically compensating for these variations during charging to increase system efficiency and regulate delivered power. In some embodiments, load variations are tracked by comparing a feedback signal to a value range and determining whether the feedback value is higher than, lower than, or within the range of values. This information is then used to modify one or more parameters associated with a power amplifier in a transmitter device.
    Type: Grant
    Filed: November 19, 2014
    Date of Patent: December 25, 2018
    Assignee: Massachusetts Institute of Technology
    Inventors: Anantha Chandrakasan, Rui Jin
  • Patent number: 10153663
    Abstract: A power transmission apparatus includes: a power transmission coil which is formed to surround a winding axis extending in the top-bottom direction, and which has a hollow formed in a center thereof; a ferrite core which has an upper surface on which the power transmission coil is disposed, and which has an opening formed therein, the opening located in the hollow in the power transmission coil when viewed from above; and a metal member located in the hollow and the opening when viewed from above the power transmission coil and the ferrite core.
    Type: Grant
    Filed: July 27, 2016
    Date of Patent: December 11, 2018
    Assignee: TOYOTA JIDOSHA KABUSHIKI KAISHA
    Inventors: Hiroaki Yuasa, Nobuhiro Kibudera
  • Patent number: 10152078
    Abstract: The present invention provides a voltage generation circuit which outputs high-precision output voltage in a wide temperature range. A semiconductor device has a voltage generation circuit. The voltage generation circuit has a reference voltage generation circuit which outputs reference voltage, and a plurality of correction circuits for generating a correction current and making it fed back to the reference voltage generation circuit. The correction circuits generate sub correction currents which monotonously increase from predetermined temperature which varies among the correction circuits toward a low-temperature side or a high-temperature side. The correction current is sum of a plurality of sub correction currents.
    Type: Grant
    Filed: June 27, 2016
    Date of Patent: December 11, 2018
    Assignee: RENESAS ELECTRONICS CORPORATION
    Inventors: Shinya Sano, Yasuhiko Takahashi, Masashi Horiguchi
  • Patent number: 10153759
    Abstract: A control chip coupled to a first input/output pin and a second input/output pin and including a first interface module, a second interface module, a first switching unit, and a control unit is provided. The first interface module includes a first pin electrically connected to the first input/output pin and a second pin. The second interface module includes a third pin. The control unit controls the first switching unit to turn on a first path between the second pin and the second input/output pin or a second path between the third pin and the second input/output pin. When the first path is turned on, the first interface module controls the voltage levels of the first and second input/output pins. When the second path is turned on, the second interface module controls the voltage level of the second input/output pin.
    Type: Grant
    Filed: October 7, 2015
    Date of Patent: December 11, 2018
    Assignee: VIA TECHNOLOGIES, INC.
    Inventors: Hao-Hsuan Chiu, Yen-Ting Lai
  • Patent number: 10146238
    Abstract: A resistorless CMOS low power voltage reference circuit is provided. The start-up circuit is used to prevent the circuit to stay in the zero state and stop working when the circuit gets out of the zero state. The self-biased VPTAT generating circuit generate the voltage VPTAT which has positive temperature coefficient. The square-law current generating circuit generates a square-law current which is proportional to ?T2 through the VPTAT. Finally, the reference voltage VREF is obtained by introducing the square-law current into the reference voltage output circuit. The reference voltage VREF of this application can realize approximative zero temperature coefficient in the temperature range of ?40° C.˜100° C. This application improves temperature characteristic which may be poorer due to temperature nonlinearity of carrier mobility based on the traditional subthreshold reference. This application can reduce the power consumption from ?W level to nW level and realize low power consumption.
    Type: Grant
    Filed: May 19, 2017
    Date of Patent: December 4, 2018
    Assignee: University of Electronic Science and Technology of China
    Inventors: Zekun Zhou, Yao Wang, Jianwen Cao, Hongming Yu, Yunkun Wang, Anqi Wang, Zhuo Wang, Bo Zhang
  • Patent number: 10148258
    Abstract: An integrated circuit and method are described for compensating for voltage droop on an integrated circuit using a power supply voltage monitoring circuit and a high-resolution adaptive clock stretching circuit. In some example embodiments, the method includes monitoring power supply voltage on an integrated circuit, detecting a voltage droop such as a dynamic loss of power supply in the integrated circuit, and stretching a current clock cycle, according to the detected voltage droop, to provide more time for logic on the integrated circuit to complete before a next clock cycle.
    Type: Grant
    Filed: September 28, 2016
    Date of Patent: December 4, 2018
    Assignee: Mellanox Technologies, Ltd.
    Inventors: Andrew Carlson, Carl Ramey
  • Patent number: 10141784
    Abstract: A power receiving device includes: a ferrite member including a plurality of pieces of ferrite at least some of which are spaced from adjacent pieces of ferrite; a power receiving coil disposed on a lower surface side of the ferrite member; and a power receiving capacitor disposed on an upper surface side of the ferrite member. The power receiving capacitor has a closed loop circuit including first and second wiring connections and a plurality of capacitor elements connected in parallel between the first wiring connection and the second wiring connection. When the power receiving capacitor and the ferrite member are viewed from the lower surface side of the ferrite member, the closed loop circuit is located behind and within a perimeter of one of the pieces of ferrite. A power transmitting device has a mirror structure to the power receiving device.
    Type: Grant
    Filed: March 9, 2016
    Date of Patent: November 27, 2018
    Assignee: TOYOTA JIDOSHA KABUSHIKI KAISHA
    Inventor: Hiroaki Yuasa