Patents Examined by Quan Tra
  • Patent number: 11329642
    Abstract: Methods and devices to improve the switching speed of radio frequency FET switch stacks are disclosed. The described methods and devices are based on bypassing drain-sources resistors when the FET switch stack is transitioning from an ON to an OFF state. Several implementations of the disclosed teachings are also presented.
    Type: Grant
    Filed: March 15, 2021
    Date of Patent: May 10, 2022
    Assignee: PSEMI CORPORATION
    Inventors: Ravindranath D. Shrivastava, Simon Willard, Peter Bacon
  • Patent number: 11322978
    Abstract: A method of energy harvester reconfiguration for a simultaneous wireless information and power transfer (SWIPT) receiver including receiving an input power from an RF signal, determining whether a Nblock-th energy block is activated based on a condition for operating the Nblock-th energy block having a maximum valid input power, among Nblock energy blocks each having a predetermined valid input power, in response to the Nblock-th energy block being determined activated, determining a number of energy harvesting circuits that are activated, among a plurality of energy harvesting circuits included in the Nblock-th energy block, based on power conversion efficiency, and reconfiguring power input in the Nblock-th energy block and the plurality of energy harvesting circuits included in the Nblock-th energy block, based on the determination and result of determination.
    Type: Grant
    Filed: October 1, 2020
    Date of Patent: May 3, 2022
    Assignee: Research & Business Foundation Sungkyunkwan University
    Inventors: Dong In Kim, Jong Ho Moon, Jong Jin Park
  • Patent number: 11320850
    Abstract: A voltage selection circuit for selecting a voltage from a plurality of input voltages comprising a plurality of diodes, each diode having a first terminal coupled to one of the input voltages, and a current sensor configured to sense a current flow through each diode, wherein the selected voltage is dependent on the sensed current flow. In operation, the circuit functions as a comparator to detect the maximum among the input voltages. The comparator decision is used to close one or more of the power switches to ensure that the load is powered from the highest input voltage.
    Type: Grant
    Filed: February 4, 2021
    Date of Patent: May 3, 2022
    Assignee: Dialog Semiconductor B.V.
    Inventor: Andrew John Myles
  • Patent number: 11323111
    Abstract: A method of signal detection includes receiving an input voltage signal; using AC (alternate current) coupling to couple the input voltage signal into a coupled voltage signal; establishing a DC (direct current) value of the coupled voltage signal using a resistor; generating a self-mixed voltage signal by performing a self-mixing of the coupled voltage signal using a pair of cross-coupling MOS (metal oxide semiconductor) transistors; generating an output voltage by applying low-pass filtering on the self-mixed voltage signal; generating a reference voltage using a reference current terminated with a reference load; and determining a logical signal by comparing the output voltage with the reference voltage.
    Type: Grant
    Filed: January 4, 2021
    Date of Patent: May 3, 2022
    Assignee: REALTEK SEMICONDUCTOR CORP.
    Inventor: Chia-Liang (Leon) Lin
  • Patent number: 11322979
    Abstract: The hydrosphere provides a natural wireless electric grid transporting energy through with a 7.5 Hz to 300 Hz bandpass. The hydrosphere grid eliminates the need for transmission lines and distribution lines operating at 50 Hz or 60 Hz worldwide. Global lightning return stroke current is sourced by the hydrosphere triggered by high voltage storm cloud conductivity. A power receiver extracts power from the Earth's hydrosphere, which serves as a current source for the power receiver. Water/moisture in the hydrosphere is conductive to ELF/SLF EM energy and functions as an electromagnetic spherical antenna that conducts broadband electromagnetic energy between 7.5 Hz and about 300 Hz. The power receiver comprises a resonant transformer that is electrically coupled to the earth's hydrosphere. The resonant transformer induces current flow from the Earth's hydrosphere. The power converts energy in ELF/SLF waves to useful form, e.g. 60 Hz AC or DC.
    Type: Grant
    Filed: December 2, 2020
    Date of Patent: May 3, 2022
    Assignee: EARTH ENERGIES, INC.
    Inventors: John Dinwiddie, Terry L. Wright
  • Patent number: 11316502
    Abstract: Systems and methods for detecting an open condition in a master-slave configuration are described. In an example, a controller can be integrated in a slave device of a master-slave configuration. The controller can be configured to activate a current source to supply a current to a pin of the slave device. The controller can be further configured to compare a voltage measured at the pin of the slave device with a reference voltage. The controller can be further configured to, based on the comparison, determine a presence or an absence of an open condition associated with the pin of the slave device. The controller can be further configured to output a signal representing the determination of the presence or the absence of the open condition to a master device.
    Type: Grant
    Filed: March 9, 2021
    Date of Patent: April 26, 2022
    Assignee: Renesas Electronics America Inc.
    Inventors: Chun Cheung, Keerthi Varman Anna Jayaprakash, Fumihito Hayashi, Yuji Ikeda
  • Patent number: 11309877
    Abstract: Disclosed are circuits and methods for a comparator with a floating capacitive supply. A capacitor is coupled between a comparator and a power supply. Two sets of electronic switches are configured in opposing operational states to shift the configuration of the circuit between a charging configuration and a decision configuration. In the charging configuration, the capacitor draws current from the power supply. In the decision configuration, the comparator pulls current from the capacitor to perform a decision. The configuration of the two sets of switches is alternated to toggle between the charging configuration and the decision configuration, allowing for the capacitor to be recharged between each decision performed by the comparator.
    Type: Grant
    Filed: January 15, 2021
    Date of Patent: April 19, 2022
    Assignee: Ethernovia Inc.
    Inventor: Klaas Bult
  • Patent number: 11309873
    Abstract: The present invention discloses a voltage level conversion circuit. A first and a second N-type driving transistors turn on when a first power voltage source supplies a high state voltage. A voltage transmission circuit transmits a first and a second input voltages having opposite levels to sources of the first and the second N-type driving transistors. A current source operates according to a second supply voltage source and has a first and a second output terminals. A first and a second connection transistors respectively couple between the drain of the first N-type driving transistor and the second output terminal and between the drain of the second N-type driving transistor and the first output terminal. The first and the second connection transistors turn on and off when the first voltage supply source supplies the high state voltage and a low state voltage.
    Type: Grant
    Filed: April 13, 2021
    Date of Patent: April 19, 2022
    Assignee: REALTEK SEMICONDUCTOR CORPORATION
    Inventor: Tsung-Yen Liu
  • Patent number: 11296597
    Abstract: A power converter circuit included in a computer system includes a switched-capacitor circuit as well as one or more bypass devices, and generates a particular voltage on a regulated power supply node. In response to situations that can result in a rapid transient of the voltage level on the regulated power supply node (e.g., upscaling or downscaling), the power converter circuit may activate the bypass devices to source or sink current from the regulated power supply node. By employing both the switched-capacitor circuit and the bypass devices, the power converter may be able to more rapidly adjust the voltage level of the regulated output supply node, as well as maintain voltage across the devices and capacitors included in the switched-capacitor circuit within specified tolerances.
    Type: Grant
    Filed: September 25, 2020
    Date of Patent: April 5, 2022
    Assignee: Apple Inc.
    Inventors: Alberto Alessandro Angelo Puggelli, Ahmed M. Sawaby
  • Patent number: 11290108
    Abstract: A bus interface bus is described. A first logical state is conveyed over the bus by a higher voltage level and a second logical state is conveyed by a lower voltage level. An output stage of the interface includes a power transistor configured to drive the lower voltage level onto the bus to convey the second logical state, and a protective device between the power transistor and the bus. The protective device couples the power transistor to the bus when turned on and limits negative voltage excursions at the power transistor when turned off. A control circuit of the interface is configured to turn on the protective device when the bus voltage is above the lower voltage level and to turn off the protective device when the bus voltage is at or below the lower voltage level.
    Type: Grant
    Filed: January 18, 2021
    Date of Patent: March 29, 2022
    Assignee: Cypress Semiconductor Corporation
    Inventors: Toru Miyamae, Kazuhiro Tomita, Koji Okada
  • Patent number: 11283350
    Abstract: A power source switching device that includes: a switch connected to a signal input terminal via a first resistor element and configured to fix a potential of the signal input terminal at a predetermined potential by adopting an ON state in a case in which a selection signal is not input; and a switch control circuit configured to perform control to place the switch in an OFF state based on a state signal indicating an operational state of a circuit that operates when supplied with power from a power source selected according to the selection signal in a case in which a potential of the selection signal is different from the predetermined potential, and to perform control to place the switch in the ON state in a case in which the selection signal is not input.
    Type: Grant
    Filed: April 27, 2021
    Date of Patent: March 22, 2022
    Assignee: LAPIS SEMICONDUCTOR CO., LTD.
    Inventor: Tetsuya Ono
  • Patent number: 11283305
    Abstract: According to one embodiment, an electronic apparatus includes a control circuitry and a transmitter. The control circuitry is configured to select a first frequency band based on channel information on at least one communication channel included in a communication frequency band of a wireless communication standard. The transmitter transmits power via an electromagnetic wave in the first frequency band.
    Type: Grant
    Filed: March 8, 2019
    Date of Patent: March 22, 2022
    Assignee: KABUSHIKI KAISHA TOSHIBA
    Inventors: Tomoko Adachi, Toshiya Mitomo
  • Patent number: 11281249
    Abstract: Aspects of the invention include a first voltage sensitive circuit including first transistors, the first transistors being coupled together so as to be operatively coupled to a first current source. A second voltage sensitive circuit includes second transistors, the second transistors being coupled together so as to be operatively coupled to a second current source, the first voltage sensitive circuit being coupled to the second voltage sensitive circuit to form a delay chain, the first and second current sources being responsive to changes in voltage of a power supply according to a voltage reference. A voltage sensitive current reference module is coupled to the first and second current sources and configured to supply the voltage reference to the first and second current sources, the voltage sensitive current reference module being responsive to changes in the voltage of the power supply.
    Type: Grant
    Filed: September 23, 2019
    Date of Patent: March 22, 2022
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Erik English, Akil Khamisi Sutton, Pawel Owczarczyk, Michael Sperling
  • Patent number: 11271475
    Abstract: Disclosed is an N:1 (where N is an integer such as 3 or higher) resonant star topology converter to generate an input supply (e.g., 1.8V) for a processor (e.g., a system-on-chip (SOC)) from a higher power supply source (e.g., 12.6V) such as a battery or other source. The resonant star topology based regulator can be realized by a combination of on-die and on-package components as opposed to voltage regulators on motherboard with discrete inductor and capacitors. In one example, capacitors of the N:1 resonant star topology are implemented as multilayer ceramic capacitors (MLCC). The architecture of the N:1 resonant star topology based regulator results in high bandwidth. For example, compared to traditional step-down voltage regulators, the N:1 resonant star topology based regulator exhibits ten times higher bandwidth.
    Type: Grant
    Filed: June 13, 2019
    Date of Patent: March 8, 2022
    Assignee: Intel Corporation
    Inventors: Rinkle Jain, Jonathan Douglas, Shivadarshan Rajeurs
  • Patent number: 11271551
    Abstract: A level shifter includes a self-initialization circuit. The self-initialization circuit judges whether the input signal and the inverted input signal received by the level shifter are invalid while a power supply voltage is powered up. If the self-initialization circuit confirms that the input signal and the inverted input signal received by the level shifter are invalid, the self-initialization circuit controls the level shifter to be maintained in a self-initializing power up state. Consequently, the output signal from the level shifter has the specified voltage level.
    Type: Grant
    Filed: May 12, 2021
    Date of Patent: March 8, 2022
    Assignee: EMEMORY TECHNOLOGY INC.
    Inventor: Huan-Min Lin
  • Patent number: 11264981
    Abstract: A method and apparatus is disclosed for maintaining a stable power supply to a circuit when activating/deactivating a switch in order to accelerate the switching time of the switch. The gate of a FET is coupled to a switch driver. The switch driver is powered by a positive power supply and a negative power supply. When the switch is to be activated/deactivated, the gate is first coupled to a reference potential (i.e., ground) for a “reset period” to reduce any positive/negative charge that has been accumulated in the FET. At the end of the reset period, the gate is then released from the reference potential and the switch driver drives the gate to the desired voltage level to either activate or deactivate the switch.
    Type: Grant
    Filed: February 1, 2021
    Date of Patent: March 1, 2022
    Assignee: pSemi Corporation
    Inventor: Chengkai Luo
  • Patent number: 11251785
    Abstract: An integrated circuit includes a first input port configured to receive a supply voltage from a switched-mode power supply (SMPS), where frequency components of the supply voltage include harmonics of a reference frequency, where the reference frequency is equal to a first frequency divided by a factor; and a spurious components cancellation circuit coupled to the first input port, where the spurious components cancellation circuit is configured to: generate a first clock signal having the reference frequency; adjust an amplitude and a phase of the first clock signal to form a compensation signal; and add the compensation signal to the supply voltage to produce a modified supply voltage with reduced frequency components at one or more harmonic frequencies of the reference frequency.
    Type: Grant
    Filed: March 29, 2021
    Date of Patent: February 15, 2022
    Assignee: Infineon Technologies AG
    Inventor: Grigory Itkin
  • Patent number: 11249504
    Abstract: Provided is a current generation circuit including a first terminal to be connected to a first external circuit; a second terminal to be connected to a second external circuit; a first resistor in which a potential is generated by the first external circuit connected through the first terminal; a second resistor in which a potential is generated by the second external circuit connected through the second terminal; a first amplifier circuit including a first positive input terminal to which the potential generated in the first resistor is supplied, and a first negative input terminal to which the potential generated in the second resistor is supplied; and a first MOS transistor having a gate connected to an output terminal of the first amplifier circuit, a source connected to the first negative input terminal, and a drain connected to a first differential current terminal.
    Type: Grant
    Filed: February 20, 2020
    Date of Patent: February 15, 2022
    Assignee: ABLIC INC.
    Inventor: Fumiyasu Utsunomiya
  • Patent number: 11251624
    Abstract: An energy efficiency control method and apparatus are provided. The method, implemented by a communications device comprising a primary power supply, a secondary power supply, and a control apparatus, includes: obtaining a current load rate of the primary power supply and a load power of the secondary power supply; determining, based on the obtained current load rate and the load power, a target output voltage of the primary power supply and a target input voltage of the secondary power supply that satisfy an energy efficiency requirement of the communications device, wherein energy efficiency of the communications device is related to the energy efficiency of the primary power supply and the energy efficiency of the secondary power supply; and controlling the primary power supply to output the target output voltage, and controlling an input voltage of the secondary power supply to be the target input voltage.
    Type: Grant
    Filed: April 23, 2021
    Date of Patent: February 15, 2022
    Assignee: Huawei Technologies Co., Ltd.
    Inventors: Jianhua Peng, Xingjie Wang, Tao Feng
  • Patent number: 11251759
    Abstract: An apparatus has four transistors. The first and third transistors each have a gate coupled to a first input terminal and second input terminal respectively, a source coupled to a current source and to a first terminal of a bias voltage source, and a substrate coupled to a second terminal of the bias voltage source. The second and fourth transistors each have a gate coupled to the first input terminal and the second input terminal respectively, a source coupled to the drain of the first and third transistors respectively, a drain coupled to a lower voltage supply and a substrate coupled to its source. The bias voltage source increases the threshold voltages of the first and third transistors above the second and fourth transistors, respectively. This ensures that the first and third transistors turn on after the second and fourth transistors, respectively.
    Type: Grant
    Filed: January 30, 2020
    Date of Patent: February 15, 2022
    Assignee: TEXAS INSTRUMENTS INCORPORATED
    Inventors: Vadim Valerievich Ivanov, Srinivas Kumar Pulijala