Abstract: Circuits, systems, and methods are described herein for increasing a hold time of a master-slave flip-flop. A flip-flop includes circuitry configured to receive a scan input signal and generate a delayed scan input signal; a master latch configured to receive a data signal and the delayed scan input signal; and a slave latch coupled to the master latch, the master latch selectively providing one of the data signal or the delayed scan input signal to the slave latch based on a scan enable signal received by the master latch.

Abstract: Disclosed herein is an apparatus that includes a data serializer including a plurality of first buffer circuits configured to receive a plurality of data, respectively, and a second buffer circuit configured to serialize the plurality of data provided from the plurality of first buffer circuits. At least one of the plurality of first buffer circuits and the second buffer circuit includes: a first circuit configured to drive a first signal node to one of first and second logic levels based on an input signal, the first circuit including a first adjustment circuit configured to adjust a driving capability of the first circuit when the first circuit drives the first signal node to the first logic level; and a second circuit configured to drive the first signal node to other of the first and second logic levels.

Abstract: A master-slave flip-flop includes a first latch, a second latch and a tristate driver. The first latch has a combined input/output that is coupled with a common node, a pm output, and an nm output. The tristate driver has pm and nm inputs coupled with the pm and nm outputs of the first latch, and a tristate output coupled with the common node. A pm input signal prevents the tristate driver from pulling the common node high, and an nm input signal prevents the tristate driver from pulling the common node low. The second latch is directly coupled with the common node. The first latch generates an nm signal and a pm signal in response to a signal on the first latch clk input and a state of the common node, wherein the pm signal and the nm signal have opposite polarities when the signal on the first latch clk input has a first value, and equal polarities when the signal on the first latch clk input has a second value.

Abstract: A processing system comprising a first sub-circuit configured to be powered by a first supply voltage and a second sub-circuit configured to be powered by a second supply voltage. The first sub-circuit comprises a general-purpose input/out register. The second sub-circuit comprises: a storage circuit configured to selectively store configuration data from the general-purpose input/out register; an input/output interface, at least one peripheral and a selection circuits to exchange signals of the peripherals, and the stored configuration data with the input/output interface. A power management circuit is configured to manage a normal operating mode, and a low-power mode during which the configuration data are maintained stored and the first sub-circuit is switched off. The power management circuit activates the low-power mode in response to receiving a command, and resumes the normal operating mode in response to a wake-up event.

Abstract: An apparatus that includes an interposer, first power connectors that are disposed on a first surface and that receive respective power inputs from one or more power sources, second power connectors that are disposed on the second surface and that receive a respective third power connecter of an integrated circuit when the integrated circuit is mounted on the second surface of the interposer, a plurality of switches formed within the interposer, control circuitry formed within the interposer, and a sequencer circuit coupled to the control input of the control circuitry and that generates a different values for a control input signal that causes the control logic of the control circuitry to generate a corresponding set of switch signals, and the plurality of different values for the control input signal are generated according to a predefined sequence to provide power to the integrated circuit according to power up sequence.

Abstract: A circuit includes a power management circuit and a memory circuit. The power management circuit is configured to receive a first control signal and a second control signal, and to supply a first supply voltage, a second supply voltage and a third supply voltage. The first control signal has a first voltage swing, and the second control signal has a second voltage swing different from the first voltage swing. The first control signal causes the power management circuit to enter a power management mode having a first state and a second state. The memory circuit is coupled to the power management circuit, and is in the first state or the second state in response to at least the first supply voltage supplied by the power management circuit.

Abstract: A delay-locked loop (DLL) and corresponding method improve frequency of a chip. The DLL comprises a first programmable delay element configured to output a first clock, a second programmable delay element configured to output a second clock a phase detector. The phase detector includes a first clock input and a second clock input. The first and second programmable delay elements are further configured, in combination, to introduce a controllable skew between the first and second clocks. The DLL is configured to input the first and second clocks to the first and second clock inputs of the phase detector, respectively. The controllable skew is configured to improve the frequency of the chip.

Abstract: Devices and methods for operating a charge pump. In some implementations, a charge pump module includes a clock circuit configured generate to a first clock signal and a second clock signal, the first clock signal having a lower frequency than the second clock signal. The charge pump module also includes a driving circuit configured to generate a first set of clock signals based on the first clock signal and a second set of clock signals based on the second clock signal, the driving circuit coupled to the clock circuit. The charge pump module further includes a charge pump core including a set of capacitances, the charge pump core configured to charge the set of capacitances based the first set of clock signals and the second set of clock signals.

Abstract: An induction cooker according to the present disclosure includes a body including a top plate on which a heating target is placed, a frame formed to surround an outer periphery of the top plate, and having a discontinuous portion being electrically discontinuous from other parts of the frame, a heating coil disposed below the top plate, and configured to inductively heat the heating target, a driver circuit configured to supply electric power to the heating coil, a power transfer coil configured to transfer electric power by magnetic resonance, and a power transfer circuit configured to supply electric power to the power transfer coil, and a power receiving device including a power receiving coil configured to receive electric power from the power transfer coil by magnetic resonance, and a load circuit configured to operate by the electric power received by the power receiving coil.

Abstract: Systems, methods, and apparatuses for receiving wireless power using a wireless power receiver client architecture are disclosed. A simplified wireless power receiver apparatus includes an energy storage device and a radio frequency (RF) transceiver including an antenna. Energy harvester circuitry is coupled to the energy storage device and the RF transceiver, and control circuitry is coupled to the energy storage device, the RF transceiver, and the energy harvester. The control circuitry causes the RF transceiver to: establish a connection with a wireless power transmitter (WPT), transmit a beacon signal to the WPT, and receive a wireless power signal from the WPT. The control circuitry causes the energy harvester to deliver at least a portion of energy of the wireless power signal to the energy storage device for storage therein. In some embodiments, a single antenna is utilized both for transmitting the beacon signal and for receiving the wireless power signal.

Abstract: An electronic device, a wireless charging device and a wireless charging method, which belong to the technical field of charging. The electronic device comprises: a receiving coil, a receiving circuit, a first switch module and a first control module, wherein the first control module is used for controlling, according to a related parameter for the magnetic coupling strength between the receiving coil and a transmitting coil of a wireless charging device, the turning on and off of at least two first switches in the first switch module, so as to adjust the number of turns of subcoils in the receiving coil that effectively work.

Abstract: An electric device includes: a first power domain; a second power domain; a third power domain, where during power-up, the third, the second, and the first power domains are configured to be powered up sequentially, where during standby-exit, the first, the second, and the third power domains are configured to be powered up sequentially; isolation paths that provide controlled signal transmission among the first, the second, and the third power domains, where each isolation path includes an isolation circuit between an input power domain and an output power domain of the isolation path; and a control circuit in the first power domain, where for each isolation path, the control circuit is configured to generate an isolation control signal for the isolation circuit, where the isolation circuit is configured enable or disable signal transmission along the isolation path.

Abstract: A radio frequency, RF, switch circuit (201, 301, 401, 501, 601, 701, 751, 801) includes at least one first PiN diode device (252, 352, 452, 552, 652, 752, 852, 945) configured to sink or source a first alternating current; and an impedance inversion circuit (222, 322, 422, 522, 622, 722, 822, 922), connected to the at least one first PiN diode device and arranged to provide a transformed impedance between a first side of the impedance inversion circuit and a second side of the impedance inversion circuit. The RF switch further includes a second diode-based device (254, 354, 454, 554, 654, 754, 854, 945) configured to source or sink a second alternating current; and a bias circuit (330, 430, 530, 630, 830, 930) connected to at least one of the at least one first PiN diode device and the second diode-based device, wherein the at least one first PiN diode device cooperates with the second diode-based device as a push-pull current circuit.

Abstract: Methods, apparatuses, and systems for wireless power transfer (WPT) in ball-and-socket type structures are provided. A ball and ball-socket structure can include conductive windings and conductive plates having a variety of shapes to optimize WPT over different angles as the ball moves or rotates within the ball-socket. One or both of capacitive coupling and inductive coupling can be incorporated.

Abstract: A cross-coupled differential activated latch circuit with circuitry comprising a plurality of n-FETs and inverters that can be implemented completely in GaN. The circuitry prevents the digital latched values on the outputs of the latch from changing unless the digital input values on the inputs are different, thus preventing common-mode voltage on the inputs from corrupting the stored latch values.

Abstract: A glitch detector includes a sensing circuit, a glitch-to-pulse generator and a comparing circuit. The sensing circuit generates a glitch voltage and at least one reference voltage based on a first power supply voltage. The glitch-to-pulse generator receives the first power supply voltage or the glitch voltage, and generates at least one pulse voltage including a pulse when the glitch occurs on the first power supply voltage. The comparing circuit generates at least one detection voltage by comparing the glitch voltage with the at least one reference voltage based on the pulse included in the at least one pulse voltage. The at least one detection voltage is activated when the glitch occurs on the first power supply voltage.

Abstract: Systems for a cascaded multiple feedback generator controller are provided. Aspects include a direct current (DC) power supply comprising a generator and a rectifier circuit connected to a load, a first voltage sensing device coupled to a first point of regulation, a second voltage sensing device coupled to a second point of regulation, a generator controller configured to receive a first voltage signal from the first voltage sensing device, receive a second voltage signal from the second voltage sensing device, determine an adjustment for the generator, the adjustment comprising a transient performance response and a voltage droop response, wherein the transient performance response is determined based on the first voltage signal, and wherein the voltage droop response is determined based on the second voltage signal, and operate the generator based on the adjustment for the generator.

Abstract: A current steering comparator includes an amplifier circuit, a bias circuit, a latch circuit, and a detector circuit. The amplifier circuit is configured to compare a first input signal with a second input signal during a comparison phase, in order to output a first signal and a second signal. The bias circuit is configured to utilize a tunable capacitor to bias the amplifier circuit during the comparison phase. The latch circuit is configured to generate a first output signal and a second output signal according to the first signal and the second signal during the comparison phase. The detector circuit is configured to detect the first output signal and the second output signal according to a predetermined clock signal to generate a control signal, in order to adjust the tunable capacitor.

Abstract: An integrated circuit for hardware security comprises a voltage glitch detection processing system comprising an oscillator circuit that generates and outputs a local oscillator clock which is a function of a supply voltage; a counter clocked by the oscillator circuit to generate at least one count value; and a capture section that synchronizes the at least one count value into a system clock domain for detecting a voltage glitch in the supply voltage.

Abstract: A wireless power system has a wireless power transmitting device such as a charging puck and a wireless power receiving device such as a battery-operated device. The charging puck may be connected to a plug via a cable. The plug may include a boot and a connector. The boot may house a printed circuit board that is positioned closer to one of the boot housing walls.