Abstract: According to an embodiment, there is provided an energy harvesting system using linear kinetic energy based on induction power generation. According to various embodiments, there may be provided an energy harvesting system using linear kinetic energy based on induction power generation, which may minimize the occasions of replacing or recharging the battery in battery-powered products by using the force or energy generated from a linearly reciprocating machine or device and may allow the battery to be charged when linear kinetic energy is generated and, otherwise, discharged, using an automatic battery charging/discharging system.

Abstract: A device for harvesting electrical energy includes a rectifier and a control device. The rectifier includes a first charging circuit for harvesting energy from a positive voltage of an energy harvester, and a second charging circuit for harvesting energy from a negative voltage of the energy harvester. The charging circuits include a common coil and a common electronic switch. Furthermore, each of the charging circuits includes a capacitor and a blocking element. Because the charging circuits use the coil jointly, the device is designed in a simple and compact manner. In addition, the energy harvesting is efficient, due to the one-stage AC-DC conversion and due to a maximum power point tracking function of the control device.

Abstract: A data storage apparatus includes storage, and a controller including an internal voltage trimming circuit and controlling the storage in response to a request from a host. The trimming circuit may include an integral circuit sampling a difference between a test voltage output by a device under test and a reference voltage, generating an integral signal by integrating a sampled signal, and including an offset cancellation unit cancelling an offset from the sampled signal, a comparison circuit generating a comparison signal by comparing the integral signal with the reference voltage, a code generation circuit receiving an initial trimming code and generating preliminary trimming codes by increasing or decreasing the initial trimming code in response to the comparison signal, and a code average signal generation circuit generating the final trimming code by averaging the preliminary trimming codes for a given time and provide the final trimming code to the storage.

Abstract: A power detection circuit for detecting powering down of a voltage domain in an integrated circuit is disclosed. The power detection circuit is placed in or near the voltage domain in the integrated circuit to provide power detection on the integrated circuit. The power detection circuit detects powering down of the voltage domain to provide an isolation enable signal to another voltage domain that interfaces with the powering down voltage domain. The isolation enable signal may be used by an isolation cell coupled to the non-powering down voltage domain to prevent corrupted logic being received from the powering down voltage domain.

Abstract: In one embodiment of a wireless power transmitter, two coils are magnetically coupled together by placing both coils on a magnetic layer. A power circuit generates an AC signal of a defined voltage magnitude that causes a current to flow through the first coil, which generates a magnetic field having a first polarity. The second coil is coupled to the first coil. Current flows through the second coil and generates a magnetic field having a second polarity that is opposite from the first polarity. Because the magnetic field generated by each coil has a different polarity, the magnetic fields attract and form a strong magnetic field that flows from the first coil to the second coil. The strong magnetic field can transfer greater amounts of power to a receiver in comparison to coil configurations that emit magnetic fields in the same direction that repel one another.

Abstract: A transmitter may include an emphasis circuit suitable for generating a first pull-down driving signal in response to first data and delayed second data, and generating a first pull-up driving signal in response to second data and delayed first data, wherein the first and second data are a differential pair; a phase skew compensation circuit suitable for compensating for a phase skew between the first pull-up driving signal and the first pull-down driving signal to generate a second pull-up driving signal and a second pull-down driving signal; a pull-up driver suitable for pull-up driving an output node in response to the second pull-up driving signal; and a pull-down driver suitable for pull-down driving the output node in response to the second pull-down driving signal.

Abstract: Described herein are reduced-power electronic circuits with wide-band energy recovery using non-interfering topologies. A resonant clock distribution network comprises a plurality of resonant clock drivers that receive at least one of a plurality of reference clock signals. An energy saving component is coupled with the plurality of resonant clock drivers. The energy saving component provides for lower energy consumption by resonating with unwanted parasitic capacitance of a load capacitance. The energy saving component and the load capacitance (LC) form a series resonant frequency that is significantly greater than a clock frequency of the plurality of resonant clock drivers, so that output clock signal paths are not interfered with and so that effects on skew are minimized.

Abstract: A level shifter circuit with an intermediate power domain and method for operating the same is disclosed. The level shifter circuit includes an input circuit, an output circuit, and an intermediate circuit. The input circuit is coupled to receive an input signal from a first voltage domain operating according to a first supply voltage, and generates a first intermediate signal. The intermediate circuit receives the first intermediate signal and generates a second intermediate signal. The output circuit receives the intermediate signal and provides an output signal into a second voltage domain operating at a second supply voltage different from the first. A voltage multiplexer is configured to provide one of the first or second supply voltages to the intermediate circuit depending on a state of the input signal.

Abstract: A chip package assembly and a chip function execution method thereof are provided. The chip package assembly includes a plurality of pins, and one of the plurality of pins is configured to receive a voltage signal. A processing circuit is configured to receive the voltage signal, where the processing circuit determines whether a voltage level of the voltage signal is a first level or a second level, to generate a first control signal according to the first level, and generate a second control signal according to the second level. A first functional circuit of a plurality of functional circuits executes a first function according to the first control signal, and a second functional circuit of the plurality of functional circuits executes a second function according to the second control signal.

Abstract: The present disclosure provides a voltage-to-time converter and method for reducing parasitic capacitance and power supply influences. The voltage-to-time converter includes: a main sampling network, a compensation sampling network, a discharge network and an over-threshold detection unit. The influence of a traditional VTC parasitic capacitance on a VTC output swing amplitude is reduced by using the compensation sampling network. A sampling common-mode level of the compensation sampling network is compensated, such that the influence of the low-frequency disturbance of a power supply voltage on a threshold of a traditional VTC threshold detection circuit is reduced. The output swing amplitude of the voltage-to-time converter of the present disclosure can reduce the influence of a parasitic capacitance. A voltage common-mode level of a VTC input end is related to a power supply voltage, which reduces a conversion error caused by the influence of the power supply voltage on a threshold.

Abstract: The present invention relates to a device and method for supporting improved communication speed in a wireless power transmission system. The present specification provides a method comprising the steps of: generating wireless power at an operating frequency; configuring n, as the number of cycles per bit, which is used for transmitting one bit at the operating frequency; aligning each bit of the data with the n cycles; causing the operating frequency to transition between differential biphases according to the value of said each bit during the n cycles; and transmitting the wireless power to a wireless power receiving device on the basis of magnetic coupling at the transitioning operating frequency.

Abstract: Systems, methods, and apparatuses for receiving wireless power using a wireless power receiver client architecture are disclosed. A simplified wireless power receiver apparatus includes an energy storage device and a radio frequency (RF) transceiver including an antenna. Energy harvester circuitry is coupled to the energy storage device and the RF transceiver, and control circuitry is coupled to the energy storage device, the RF transceiver, and the energy harvester. The control circuitry causes the RF transceiver to: establish a connection with a wireless power transmitter (WPT), transmit a beacon signal to the WPT, and receive a wireless power signal from the WPT. The control circuitry causes the energy harvester to deliver at least a portion of energy of the wireless power signal to the energy storage device for storage therein. In some embodiments, a single antenna is utilized both for transmitting the beacon signal and for receiving the wireless power signal.

Abstract: A driving device of a semiconductor switch includes a semiconductor switch configured to perform a switching operation by a gate driving voltage, and transfer a main power connected to a first switch terminal, to a load connected to a second switch terminal; a control signal generation circuit configured to detect a change in a control signal input power and generate and output a corresponding control signal, based on a lower negative voltage between negative voltages of the main power and the control signal input power; a control signal detection circuit configured to detect the control signal and output a corresponding driving control signal; a gate driving voltage generation circuit configured to be driven by the driving control signal and output the gate driving voltage; and an internal power generation circuit configured to be supplied with the main power, and generate a power supply voltage.

Abstract: Embodiments include a power conversion circuit comprising first and second semiconductor switches, and a drive circuit configured to create a period of operational overlap for the first and second switches by setting a gate voltage of the first switch to an intermediate value above a threshold voltage of the first switch, during turn-on and turn-off operations of the second switch. Embodiments also include a method of operating first and second semiconductor devices, comprising: reducing a gate voltage of the first device to an intermediate value above a threshold voltage while the second device is off; turning off the first device after the second device is on; increasing the gate voltage of the first device to the intermediate value while the second device is on; and fully turning on the first device after the second device is off.

Abstract: Disclosed herein is an apparatus that includes a data serializer including a plurality of first buffer circuits configured to receive a plurality of data, respectively, and a second buffer circuit configured to serialize the plurality of data provided from the plurality of first buffer circuits. At least one of the plurality of first buffer circuits and the second buffer circuit includes: a first circuit configured to drive a first signal node to one of first and second logic levels based on an input signal, the first circuit including a first adjustment circuit configured to adjust a driving capability of the first circuit when the first circuit drives the first signal node to the first logic level; and a second circuit configured to drive the first signal node to other of the first and second logic levels.

Abstract: Techniques and apparatus for selecting a maximum input supply voltage from multiple input power supplies. An example maximum input supply selection circuit includes a parallel array of comparators and selection logic to select the maximum input supply voltage, supply present detectors, comparator settling logic including a warm-up delay timer to provide for comparator settling, and comparator enable logic for disabling all comparators and entering an ultra-low power mode.

Abstract: Circuitry and processes are disclosed that use conventional electronic circuits (comprising, for example, phase locked loops, pulse width modulators, phase modulators, digital logic gates, etc.) to enable quantum algorithms. Such circuitry and processes achieve the requirement for non-quantum devices to enable quantum algorithms: the tensor product entanglement of signals representing quantum states. Such circuitry and processes are readily usable by current Electronic Design Automation tools, to design, verify and emulate applications such as fast, very large number factoring for use in decryption. Also, the independent Claims concisely signify embodiments of the claimed inventions.

Abstract: Radio frequency (RF) mixer circuits having a complementary frequency multiplier module that requires no balun to multiply a lower frequency base oscillator signal to a higher frequency local oscillator (LO) signal, and which has a significantly reduced IC area compared to balun-based frequency multipliers. In one embodiment, the complementary frequency multiplier module includes a complementary pair of FETs controlled by an applied base oscillator signal. The complementary FETs are coupled to a common-gate FET amplifier and alternate becoming conductive in response to the base oscillator signal. The alternating switching of the complementary FETs in response to the opposing phases of the base oscillator signal cause the common-gate FET amplifier to output a higher frequency local oscillator (LO) signal. The LO signal is coupled to the LO input of a mixer or mixer core of a type suitable for use in conjunction with a frequency multiplier.

Abstract: A circuit with a first transistor includes a first current electrode coupled to a first voltage supply, a second current electrode coupled to a first circuit node, and a gate electrode coupled to receive a first input signal. A second transistor includes a first current electrode coupled to the second current electrode of the first transistor, a second current electrode, and a gate electrode coupled to receive a first bias voltage. A third transistor includes a first current electrode coupled to the second current electrode of the second transistor, a second current electrode coupled to a second circuit node, and a gate electrode. A fourth transistor includes a first current electrode coupled to the second circuit node, a second current electrode coupled to a third circuit node, and a gate electrode coupled to receive a second bias voltage. The gate electrode of the third transistor is coupled to the third circuit node.

Abstract: An input circuit includes an input stage having an input node and a direct-current (DC) amplifier coupled to the input node. The input circuit also includes an alternating-current (AC) amplifier coupled to an output node of the DC amplifier. The input circuit also includes a capacitor coupled between the input node and the output node of the DC amplifier. The input circuit also includes a voltage divider coupled to the DC amplifier and the AC amplifier. The voltage divider includes first resistor associated with the DC amplifier and a second resistor associated with the AC amplifier, where the first resistor is larger than the second resistor.