Patents Examined by Quoc D. Hoang
  • Patent number: 11329246
    Abstract: An organic light emitting diode panel and a fabrication method thereof are provided. The organic light emitting diode panel includes a substrate; a pixel defining layer disposed over a portion of the substrate; an organic light emitting diode device and an auxiliary cathode contacting device disposed over the substrate, wherein the organic light emitting diode device includes an anode layer, a hole injecting layer, a hole transporting layer, a light emitting layer, and an electron transporting layer sequentially formed over a portion of the substrate, and the auxiliary cathode contacting device includes an auxiliary cathode and a conductive contact sequentially formed over another portion of the substrate; a conductive contact, including a conductive mixture consisting of the electron transporting layer and a solvent material used to dissolve the electron transporting layer; and a transparent electrode layer, covering the electron transporting layer, the pixel defining layer, and the conductive contact.
    Type: Grant
    Filed: November 22, 2019
    Date of Patent: May 10, 2022
    Inventor: Jinxiang Chen
  • Patent number: 11329013
    Abstract: Interconnected substrate arrays, microelectronic packages, and methods for fabricating microelectronic packages for fabricating microelectronic packages utilizing interconnected substrate arrays containing integrated electrostatic discharge (ESD) protection grids are provided. In an embodiment, the method includes obtaining an interconnected substrate array having an integrated ESD protection grid. The ESD protection grid includes, in turn, ESD grid lines at least partially formed in singulation streets of an interconnected substrate array and electrically coupling die attachment regions of the substrate array to one or more peripheral machine ground contacts. Array-level fabrication steps are performed to produce an interconnected package array utilizing the interconnected substrate array, while electrically coupling the die attachment regions to electrical ground through the ESD protection grid during at least one of the array-level fabrication steps.
    Type: Grant
    Filed: May 28, 2020
    Date of Patent: May 10, 2022
    Assignee: NXP USA, Inc.
    Inventors: James Cotronakis, Jose Luis Suarez, Eduard Jan Pabst
  • Patent number: 11322447
    Abstract: A semiconductor package is fabricated by attaching a first component to a second component. The first component is assembled by forming a first redistribution structure over a substrate. A through via is then formed over the first redistribution structure, and a die is attached to the first redistribution structure active-side down. The second component includes a second redistribution structure, which is then attached to the through via. A molding compound is deposited between the first redistribution structure and the second redistribution structure and further around the sides of the second component.
    Type: Grant
    Filed: March 6, 2020
    Date of Patent: May 3, 2022
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Po-Hao Tsai, Po-Yao Chuang, Meng-Liang Lin, Yi-Wen Wu, Shin-Puu Jeng, Techi Wong
  • Patent number: 11322563
    Abstract: Described is an electroluminescent device including an array substrate having a thin-film transistor formed thereon, an organic insulating layer formed on the array substrate having the thin-film transistor formed thereon, barriers disposed on the organic insulating layer, an anode formed on the organic insulating layer between the barriers to thus be electrically connected to the thin-film transistor and configured to cover at least a portion of the barriers, a light-emitting layer formed on the anode, and a cathode formed on the light-emitting layer, thus exhibiting superior emission efficiency and a wide viewing angle. A method of making or manufacturing the electroluminescent device is also described.
    Type: Grant
    Filed: February 5, 2019
    Date of Patent: May 3, 2022
    Assignee: Dongwoo Fine-Chem Co., Ltd.
    Inventors: Hun-Sik Kim, Jong-Soo Lee
  • Patent number: 11322441
    Abstract: A semiconductor storage device according to an embodiment includes: an array chip having a memory cell array; a circuit chip having a circuit electrically connected to a memory cell; and a metal pad bonding the array chip and the circuit chip together. The metal pad includes an impurity. A concentration of the impurity is lowered as separating in a depth direction apart from a surface in a thickness direction of the metal pad.
    Type: Grant
    Filed: September 4, 2020
    Date of Patent: May 3, 2022
    Assignee: Kioxia Corporation
    Inventor: Satoshi Wakatsuki
  • Patent number: 11322482
    Abstract: A component carrier with a first stack and a second stack. The first stack includes at least one first electrically insulating layer structure and at least one first electrically conductive layer structure having a first connection body with a first exposed planar electrically conductive surface. The second stack includes at least one second electrically insulating layer structure and at least one second electrically conductive layer structure having a second connection body with a second exposed planar electrically conductive surface. The first stack and the second stack are connected with each other so that the first exposed planar electrically conductive surface and the second exposed planar electrically conductive surface are connected to establish a vertical two-dimensional electrically conductive connection.
    Type: Grant
    Filed: June 4, 2020
    Date of Patent: May 3, 2022
    Assignee: AT&S Austria Technologie & Systemtechnik Aktiengesellschaft
    Inventors: Bernhard Reitmaier, Sebastian Sattler, Erich Schlaffer
  • Patent number: 11322723
    Abstract: A packaging structure, a display component and a display device are provided by the present disclosure. The packaging structure includes: a substrate; a light-emitting unit arranged on the substrate; a packaging layer, by which the light-emitting unit is packaged on the substrate; and a water-absorbing layer which is arranged in the packaging layer and completely wrapped by the packaging layer.
    Type: Grant
    Filed: October 18, 2018
    Date of Patent: May 3, 2022
    Assignee: BOE TECHNOLOGY GROUP CO., LTD.
    Inventor: Hongfei Cheng
  • Patent number: 11302633
    Abstract: A fuse latch of a semiconductor device is disclosed. The fuse latch of the semiconductor device includes a plurality of PMOS transistors and a plurality of NMOS transistors. The fuse latch includes PMOS transistors and NMOS transistors configured to latch fuse cell data. In the fuse latch, the plurality of PMOS transistors and the plurality of NMOS transistors are arranged in a shape of two lines in each active region in a second direction.
    Type: Grant
    Filed: July 14, 2020
    Date of Patent: April 12, 2022
    Assignee: SK hynix Inc.
    Inventor: Duk Su Chun
  • Patent number: 11302652
    Abstract: A semiconductor package includes a metallic pad and leads spaced from the metallic pad by a gap, the metallic pad including a roughened surface. The semiconductor package further includes a semiconductor die including bond pads, and an adhesive between the roughened surface of the metallic pad and the semiconductor die, therein bonding the semiconductor die to the metallic pad, wherein the adhesive includes a resin. The metallic pad further includes a groove surrounding the semiconductor die on the roughened surface, the groove having a surface roughness less than a surface roughness of the roughened surface of the metallic pad.
    Type: Grant
    Filed: December 20, 2019
    Date of Patent: April 12, 2022
    Assignee: TEXAS INSTRUMENTS INCORPORATED
    Inventors: ChienHao Wang, Bob Lee, YuhHarng Chien
  • Patent number: 11302756
    Abstract: A display unit, a display unit manufacturing method, and an organic light emitting diode display device are provided. The display unit includes: a substrate; a thin film transistor layer disposed above the substrate; an anode metal layer disposed above the thin film transistor layer; a pixel definition layer disposed above the anode metal layer; a light emitting structure disposed above the pixel definition layer. The pixel definition layer includes a first lamination layer and a second lamination layer disposed above the first lamination layer. Desiccants are distributed evenly in the second lamination layer.
    Type: Grant
    Filed: December 29, 2018
    Date of Patent: April 12, 2022
    Assignee: WUHAN CHINA STAR OPTOELECTRONICS SEMICONDUCTOR DISPLAY TECHNOLOGY CO., LTD.
    Inventors: Ming Xiang, Shoucheng Wang
  • Patent number: 11296033
    Abstract: The invention discloses a fan-out multi-device hybrid integrated flexible micro-system and an associated fabrication method in the field of microelectronics. The flexible microsystem uses microelectromechanical system (MEMS) chips and/or integrated circuit (IC) chips as the device units, flexible isolation trenches filled with flexible polymer as a flexible connection between the device units, and metal wiring layers to provide electrical interconnections between the device units. The disclosed multi-device hybrid integrated flexible micro-system completed by a fan-out method not only retains excellent electrical performance of silicon-based devices, but also realizes flexibility of the overall micro-system, and has stable structure and reliable performance.
    Type: Grant
    Filed: December 11, 2018
    Date of Patent: April 5, 2022
    Assignee: Peking University
    Inventors: Wei Wang, Xiao Dong
  • Patent number: 11289683
    Abstract: Provided are an organic light-emitting diode (OLED) and an organic light-emitting device including the same. The OLED includes a first electrode, an organic emissive layer which includes a plurality of convex curves or a plurality of concave curves in a light-emitting region and of which a slope of an inclined plane of an upper region with respect to a horizontal line dividing a height of the plurality of convex curves into halves is greater than a slope of an inclined plane of a lower region thereof, and a second electrode provided on the organic emissive layer. Accordingly, the OLED and the organic light-emitting device including the same are capable of improving current efficiency.
    Type: Grant
    Filed: June 10, 2020
    Date of Patent: March 29, 2022
    Assignee: LG Display Co., Ltd.
    Inventors: Ji-Hyang Jang, So-Young Jo, Won-Hoe Koo
  • Patent number: 11282790
    Abstract: The present disclosure relates to a semiconductor device with a composite landing pad. The semiconductor device includes a first dielectric layer disposed over a semiconductor substrate. The semiconductor device also includes a lower metal plug and a barrier layer disposed in the first dielectric layer. The lower metal plug is surrounded by the barrier layer. The semiconductor device further includes an inner silicide portion disposed over the lower metal plug, and an outer silicide portion disposed over the barrier layer. A topmost surface of the outer silicide portion is higher than a topmost surface of the inner silicide portion.
    Type: Grant
    Filed: September 9, 2020
    Date of Patent: March 22, 2022
    Assignee: NANYA TECHNOLOGY CORPORATION
    Inventor: Chun-Cheng Liao
  • Patent number: 11276660
    Abstract: A semiconductor device package includes an electronic component, a first passivation layer having an inner surface surrounding the electronic component, and a conductive layer disposed on the inner surface of the first passivation layer. The electronic component has a first surface, a second surface opposite the first surface, and a lateral surface extended between the first surface and the second surface. The conductive layer has a relatively rough surface. A method of manufacturing a semiconductor device package is also disclosed.
    Type: Grant
    Filed: November 27, 2019
    Date of Patent: March 15, 2022
    Assignee: ADVANCED SEMICONDUCTOR ENGINEERING, INC.
    Inventor: Chih Cheng Lee
  • Patent number: 11270882
    Abstract: A film formation apparatus is configured to supply mist of a solution to a surface of a substrate so as to epitaxially grow a film on the surface of the substrate. The film formation apparatus may be provided with: a furnace configured to house and heat the substrate; a reservoir configured to store the solution; a heater configured to heat the solution in the reservoir; an ultrasonic transducer configured to apply ultrasound to the solution in the reservoir so as to generate the mist of the solution in the reservoir; and a mist supply path configured to carry the mist from the reservoir to the furnace.
    Type: Grant
    Filed: January 13, 2020
    Date of Patent: March 8, 2022
    Assignees: DENSO CORPORATION, NATIONAL UNIVERSITY CORPORATION KYOTO INSTITUTE OF TECHNOLOGY
    Inventors: Tatsuji Nagaoka, Hiroyuki Nishinaka, Daisuke Tahara, Masahiro Yoshimoto
  • Patent number: 11264243
    Abstract: A diffuser includes a diffuser element made of silicon carbide having conductivity, conductive holding members for holding the diffuser element, conductive gaskets that seal between the diffuser element and the holding members. Static electricity on the diffuser element is eliminated through the gaskets, and the holding members.
    Type: Grant
    Filed: June 30, 2020
    Date of Patent: March 1, 2022
    Assignee: COORSTEK KK
    Inventor: Hiroki Watanabe
  • Patent number: 11257713
    Abstract: A method for manufacturing an interposer board without a feature layer structure according to an embodiment of the present invention may include preparing a temporary carrier; forming an edge seal for the temporary carrier; laminating an insulating material onto upper and lower surfaces of the temporary carrier to form an insulating layer; forming a via on the insulating layer, filling the via with a metal; and removing the edge seal and removing the temporary carrier. An interposer board without a feature layer structure according to an embodiment of the present invention may include an insulating layer and a via-post layer embedded in the insulating layer, wherein the via-post has an end used as a pad.
    Type: Grant
    Filed: October 19, 2020
    Date of Patent: February 22, 2022
    Assignee: Zhuhai ACCESS Semiconductor Co., Ltd
    Inventors: Xianming Chen, Min Gu, Benxia Huang, Lei Feng, Bingsen Xie
  • Patent number: 11251116
    Abstract: The present disclosure relates to a semiconductor module, especially a power semiconductor module, in which the heat dissipation is improved and the power density is increased. The semiconductor module may include at least two electrically insulating substrates, each having a first main surface and a second main surface opposite to the first main surface. On the first main surface of each of the substrates, at least one semiconductor device is mounted. An external terminal is connected to the first main surface of at least one of the substrates. The substrates are arranged opposite to each other so that their first main surfaces are facing each other.
    Type: Grant
    Filed: February 24, 2020
    Date of Patent: February 15, 2022
    Assignee: HUAWEI TECHNOLOGIES CO., LTD.
    Inventors: Hamit Duran, Junfu Hu
  • Patent number: 11251138
    Abstract: In described examples of an integrated circuit (IC) there is a substrate of semiconductor material having a first region with a first transistor formed therein and a second region with a second transistor formed therein. An isolation trench extends through the substrate and separates the first region of the substrate from the second region of the substrate. An interconnect region having layers of dielectric is disposed on a top surface of the substrate. A dielectric polymer is disposed in the isolation trench and in a layer over the backside surface of the substrate. An edge of the polymer layer is separated from the perimeter edge of the substrate by a space.
    Type: Grant
    Filed: December 17, 2019
    Date of Patent: February 15, 2022
    Assignee: TEXAS INSTRUMENTS INCORPORATED
    Inventors: Scott Robert Summerfelt, Thomas Dyer Bonifield, Sreeram Subramanyam Nasum, Peter Smeys, Benjamin Stassen Cook
  • Patent number: 11239076
    Abstract: A film forming method includes forming an amorphous semiconductor film on a recess, forming a first polycrystalline semiconductor film by performing heat treatment on the amorphous semiconductor film, and forming a second polycrystalline semiconductor film on the first polycrystalline semiconductor film formed by the heat treatment.
    Type: Grant
    Filed: March 11, 2020
    Date of Patent: February 1, 2022
    Assignee: TOKYO ELECTRON LIMITED
    Inventors: Yutaka Motoyama, Hiroyuki Hayashi