Patents Examined by R. Bruce Breneman
  • Patent number: 5902406
    Abstract: A low pressure CVD system comprising an inner tube having an upper end and a lower end opened, and made of a silicon carbide material, an outer tube including a circumferential wall surrounding an outer periphery of the inner tube with a predetermined spacing, an upper wall closing an upper end of the circumferential wall and a flange provided at a lower portion thereof, the outer tube having a lower end opened, a base portion for supporting the inner tube and the outer tube at the lower ends thereof, and for providing hermetic sealing between the lower end of the outer tube and the base portion, the base portion having a central portion formed with an opening, a lid provided for opening and shutting the opening in the base portion, and a furnace wall surrounding the circumferential wall and the upper wall of the outer tube, the furnace wall having a heater arranged on an inner side thereof wherein the outer tube is made of a silicon carbide material, and padding of a silicon carbide material is formed at a c
    Type: Grant
    Filed: March 14, 1997
    Date of Patent: May 11, 1999
    Assignee: Asahi Glass Company Ltd.
    Inventors: Taroh Uchiyama, Yukio Yoshikawa, Takashi Tsukamoto, Jiro Nishihama
  • Patent number: 5900163
    Abstract: A method for etching a layer of a microelectronic structure includes the steps of masking the layer to be etched so that predetermined portions of the layer are exposed, and providing an etching gas. An additional gas is also provided wherein the additional gas generates a compound having a carbene structure when exposed to a plasma discharge. A plasma of the etching gas and the additional gas is generated to thereby etch the exposed portions of the layer and to form the compound having a carbene structure. A polymer can thus be formed from the compound having the carbene structure on the sidewalls of the etched portions of the layer. Accordingly, the profile of the etched layer can be improved.
    Type: Grant
    Filed: January 16, 1997
    Date of Patent: May 4, 1999
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Whi-kun Yi, Dai-sik Moon, Sung-kyeong Kim, Kyung-hoon Kim, Gyu-hwan Kwag
  • Patent number: 5900065
    Abstract: In an apparatus for the deposition of polycrystalline diamond on large, flat substrates (3) by the plasma method, with a vacuum chamber (4); with locks for the inward and outward transfer of the substrates; with a device installed in the chamber (4) for conveying the substrates (3) through at least one, preferably through two treatment stations; with hot-filament sources (5, 5', . . . ) forming a first group, installed above the plane of the substrates; with microwave plasma sources (8, 8', . . . ) forming a second group; with an electrode (11) fed with radio frequency underneath the plane of the substrates for generating a bias voltage; and with gas feed pipes (6, 9) opening into the vacuum chamber (4), the hot-filament arrangements (5, 5', . . . ), designed as linear sources, are arranged transversely to the substrate transport direction (a) and form a first coating zone (Z.sup.1), where the microwave plasma sources (8, 8', . . .
    Type: Grant
    Filed: August 5, 1997
    Date of Patent: May 4, 1999
    Assignee: Leybold Systems GmbH
    Inventors: Michael Liehr, Claus-Peter Klages, Gunter Brauer
  • Patent number: 5895530
    Abstract: A method and apparatus for directing a process gas through a wafer processing apparatus, such as a vapor deposition chamber is provided. The apparatus comprises a pumping plate (4) defining a central opening (62) surrounding the wafer (W) and having an upper surface (64) facing the processing chamber (12) and a opposite, lower surface (66) facing a pumping channel (14). The plate defines a plurality of circumferentially spaced gas holes (90) extending between the first and second surfaces for discharging process gases from the chamber into the pumping channel. The gas holes are essentially straight so that they flow directly through the pumping plate, thereby minimizing the residence time of the gases within the processing chamber and reducing the time required to clean the gas holes. In addition, the gas holes extend in a radially outward direction relative to the central opening to substantially uniformly discharge the gas from the processing chamber.
    Type: Grant
    Filed: February 26, 1996
    Date of Patent: April 20, 1999
    Assignee: Applied Materials, Inc.
    Inventors: Ashish Shrotriya, Todd C. Bryant
  • Patent number: 5895551
    Abstract: The present invention discloses a plasma etching apparatus which can protect the surface of the wafer from a damage due to collisions among the etching ions and can also process a plurality of wafers only by one-time plasma generation. In the etching apparatus of the present invention, a plurality of wafers are loaded in the chamber by a plurality of wafer support members which are located vertically round the gas dispersion tube used as a cathode electrode, and magnetic field formation means are provided to form a magnetic field around each wafer.
    Type: Grant
    Filed: April 25, 1997
    Date of Patent: April 20, 1999
    Assignee: Hyundai Electronics Industries Co., Ltd.
    Inventor: Chang Heon Kwon
  • Patent number: 5895271
    Abstract: A metal film forming method by which a metal film having a desired pattern can be formed with good reproducibility and satisfactory precision. In a metal film forming method for forming a metal film into the desired pattern on a surface of an object by the lift-off method, a resist layer is laminated on the surface of the object, the resist layer is exposed to light with the desired pattern and it is developed. Radio frequency sputtering is then performed against the resist layer so that the opening is deformed into a shape which is suited for the lift-off process. A metal film is then laminated on the surfaces of the resist layer and the metal film forming object. Then the resist layer is subjected to lift-off processing, whereby the metal film can be formed with good precision and satisfactory reproducibility. In this way, such a metal film forming method can be realized that a metal film having the desired pattern can be formed with good reproducibility and satisfactory precision.
    Type: Grant
    Filed: December 27, 1995
    Date of Patent: April 20, 1999
    Assignee: Sony Corporation
    Inventors: Kiyoshi Hasegawa, Hiroshi Ozaki
  • Patent number: 5895223
    Abstract: A method for etching nitride is provided, by which the etching rate and the roughness of the etching surface can be powerfully controlled, and by which the etching depth can be in-situ monitored. The etching method comprises the steps of: (i) coating a first electrode on a nitride chip; (ii) mounting the nitride chip on a holding device; (iii)dipping the holding device, the nitride chip and the first electrode in electrolysis liquid; (iv) irradiating the nitride chip with a UV light having a wavelength shorter than 254 nm; and (v) connecting the first electrode to a second electrode dipped in the electrolysis liquid by a galvanometer to in-situ monitor the etching current, so as to in-situ control the etching depth.
    Type: Grant
    Filed: December 10, 1997
    Date of Patent: April 20, 1999
    Assignee: Industrial Technology Research Institute
    Inventors: Lung-Han Peng, Chih-Wei Chuang, Jin-Kuo Ho, Chin-Yuan Chen
  • Patent number: 5893982
    Abstract: A method of preventing edge stain in silicon wafers from the edge polishing step with an alkaline slurry, the method consisting of formation of an oxide layer by an annealing step in the presence of oxygen prior to edge polishing.
    Type: Grant
    Filed: January 8, 1997
    Date of Patent: April 13, 1999
    Assignee: Seh America, Inc.
    Inventors: Masami Nakano, Jim Woodling
  • Patent number: 5891243
    Abstract: In a process for growing a ZnSe crystal by an MBE or MOCVD process, N.sub.2 gas dissociated by electromagnetic waves and vapor In are prepared at a ratio of N:In being 2:1. The atomic gases may be prepared by decomposing InN at a high temperature with electromagnetic irradiation and adding N.sub.2 gas to the decomposed product. The atomic gases are fed onto a substrate in a crystal growth region, so as to simultaneously dope ZnSe with In and N at a ratio of 1:2. A n-type dopant In substitutionally occupying a position of Zn makes a 1:1 couple with a p-type dopant N substitutionally occupying a position of Se, and another one N atom coordinates near the atomic couple and serves as an acceptor. As a result, the acceptor is kept in activated state up to higher concentration, and the ZnSe crystal can be heavily doped with the p-type dopant N.
    Type: Grant
    Filed: August 7, 1997
    Date of Patent: April 6, 1999
    Assignee: Japan Science and Technology Corporation
    Inventor: Hiroshi Yoshida
  • Patent number: 5891252
    Abstract: A plasma processing apparatus in which power consumption is reduced, which can generate uniform plasma in a large range and in which minute processing in high etching selectivity and in high aspect ratio is enabled is disclosed. High density plasma is generated in a vacuum vessel housing a processed sample utilizing an electron cyclotron resonance phenomenon caused by an electromagnetic wave in an ultra-high frequency band and a magnetic field and the surface of the processed sample is etched using this plasma. An electromagnetic wave in an ultra-high frequency band for generating plasma is radiated from a planar conductive plate consisting of graphite or silicon which is arranged opposite to the surface of the processed sample into space inside the vacuum vessel. High density plasma in the low degree of dissociation can be generated by using an electromagnetic wave in an ultra-high frequency band and as a result, the controllability of etching reaction can be enhanced.
    Type: Grant
    Filed: December 13, 1996
    Date of Patent: April 6, 1999
    Assignee: Hitachi, Ltd.
    Inventors: Ken'etsu Yokogawa, Tetsuo Ono, Kazunori Tsujimoto, Naoshi Itabashi, Masahito Mori, Shinichi Tachi, Keizo Suzuki
  • Patent number: 5888908
    Abstract: A method is provided for reducing the reflectivity of a metal layer prior to photolithography. A thin buffer layer, such as oxide, can be deposited over the metal layer. A short plasma etch is performed in order to roughen, but not completely remove, the thin oxide layer. This roughened layer significantly reduces the reflectivity of the underlying metal layer. As an alternative, the brief plasma etch can be applied directly to the metal layer, which results in a significant roughening of its upper surface. This also reduces the reflectivity of the metal layer.
    Type: Grant
    Filed: April 28, 1995
    Date of Patent: March 30, 1999
    Assignee: STMicroelectronics, Inc.
    Inventors: Gregory Joseph Stagaman, Michael Edward Haslam
  • Patent number: 5888304
    Abstract: This invention provides a method and apparatus for supporting a wafer in a processing chamber, where the wafer is supported and heated from below via a heater pedestal having a diameter larger than that of the wafer. A process fluid flowing downward toward the top of the wafer is inhibited from depositing near the wafer edge by a shadow ring. The shadow ring, which is placed over but does not contact the wafer, physically masks an annular strip of the wafer near its edge. The shadow ring inhibits deposition of process fluides on the wafer in two distinct ways. First, the shadow ring physically obstructs process gas, flowing downward from above the wafer, from depositing on the masked portion of the wafer. Second, the shadow ring is used to direct a flow of a purge gas to inhibit process gas from seeping under the shadow ring and depositing near the wafer edge. A purge gas manifold is defined by a cylindrical annulus located concentrically below the shadow ring and circumscribing the heater pedestal.
    Type: Grant
    Filed: April 2, 1996
    Date of Patent: March 30, 1999
    Assignee: Applied Materials, Inc.
    Inventors: Salvador P. Umotoy, Alan F. Morrison, Karl A. Littau, Richard A. Marsh, Lawrence Chung-Lai Lei, Dale DuBois
  • Patent number: 5888906
    Abstract: A method of removing an oxide layer from an article. The article is located in a reaction chamber. An interhalogen compound reactive with the oxide layer is introduced into the reaction chamber. The interhalogen compound forms volatile by-product gases upon reaction with the oxide layer. For compounds that form volatile chlorides, bromides or iodides, a reducing gas, such as for example hydrogen, ammonia, amines, phosphine, silanes, and higher silanes, may optionally be added simultaneously with the interhalogen to form a volatile by-product. Unreacted interhalogen compound and volatile by-product gases are removed from the reaction chamber. In one embodiment, the temperature in the reaction chamber may be elevated prior to or after introducing the interhalogen compound. In another embodiment, a metal layer is deposited in-situ on a portion of the article within the reaction chamber.
    Type: Grant
    Filed: September 16, 1996
    Date of Patent: March 30, 1999
    Assignee: Micron Technology, Inc.
    Inventors: Gurtej S. Sandhu, Donald L. Westmoreland
  • Patent number: 5885404
    Abstract: A pedestal for a semiconductor device etching system includes a pedestal body having a circumferential recess. The recess includes a cutaway area extending radially inwardly therefrom. The pedestal further includes a sealing ring configured to mate with the pedestal body recess. The sealing ring includes a radially inwardly-extending projection that resides within the cutaway area of the recess. Because the sealing ring projection fits within and is retained by the cutaway area of the recess, the sealing ring remains in place upon removal of the mounted wafer even if it adheres somewhat to the wafer.
    Type: Grant
    Filed: November 4, 1997
    Date of Patent: March 23, 1999
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Sang-ho Kim, Tae-hyung Lim
  • Patent number: 5885358
    Abstract: A gas injection system for injecting gases into a plasma reactor having a vacuum chamber with a sidewall, a pedestal for holding a semiconductor wafer to be processed, and a RF power applicator for applying RF power into the chamber. The gas injection system includes at least one gas supply containing gas, a gas distribution apparatus which has at least one slotted aperture facing the interior of the chamber, and one or more gas feed lines connecting the gas supply or supplies to the gas distribution apparatus. A preferred embodiment of a radial gas distribution apparatus in accordance with the present invention is disposed in the chamber sidewall and includes plural gas distribution nozzles each with a slotted aperture facing an interior of the chamber. Gas feed lines are employed to respectively connect each gas distribution nozzle to separate ones of the gas supplies.
    Type: Grant
    Filed: July 9, 1996
    Date of Patent: March 23, 1999
    Assignee: Applied Materials, Inc.
    Inventors: Dan Maydan, Steve S. Y. Mak, Donald Olgado, Gerald Zheyao Yin, Timothy D. Driscoll, James S. Papanu, Avi Tepman
  • Patent number: 5885355
    Abstract: A semiconductor fabrication apparatus having a process chamber and a handler which is provided for loading wafers into the process chamber or unloading wafers therefrom, comprising a plurality of switches for detecting positions of the handler and for generating detection signals in accordance with the positions; and an indicator for indicating normal operations of the switches. The indicator has relays operated in accordance with a voltage level of each of the detection signals; and LEDs associated with each of the relays, for identifying a normal operation of the handler. By confirming the conductive/nonconductive state of the LED, the operator can easily determine if the switches are accurately detecting the position of a load fork and/or an aligning plate.
    Type: Grant
    Filed: December 26, 1996
    Date of Patent: March 23, 1999
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Byoung-Soo Song, Chan-Il Yu
  • Patent number: 5885899
    Abstract: A method of forming interlevel studs in an insulating layer on a semiconductor wafer. First, a conformal BPSG layer is formed on a Front End of the Line (FEOL) semiconductor structure. Vias are opened through the BPSG layer to the FEOL structure. A layer of poly is formed (deposited) on the BPSG layer, filling the vias. The poly layer may be insitu doped poly or implanted after it is deposited. The wafer is annealed to diffuse dopant from the poly to form diffusions wherever the poly contacts the substrate. A non-selective slurry of colloidal silica and at least 1% ammonium hydroxide is used to chem-mech polish the poly from the BPSG layer and, simultaneously, planarize the BPSG layer.
    Type: Grant
    Filed: November 14, 1995
    Date of Patent: March 23, 1999
    Assignee: International Business Machines Corporation
    Inventors: Michael David Armacost, David Mark Dobuzinsky, Jeffery Peter Gambino, Mark Anthony Jaso
  • Patent number: 5882402
    Abstract: A method and system for determining a diameter of a silicon single crystal being pulled from a silicon melt contained in a heated crucible. The melt has a surface with a meniscus visible as a bright area adjacent the pulled crystal. A camera generates an image of the interior of the crucible including a portion of the bright area adjacent the crystal. Image processing circuitry defines a central window region of the image having an elliptical shape at a position corresponding to an approximate center of the crystal and processes the image as a function of its pixel values to detect edges within the central window region. The image processing circuitry further groups the detected edges to define an object in the image corresponding to the crystal, determines a dimension of the defined object and determines an approximate diameter of the crystal as a function of the determined dimension of the defined object.
    Type: Grant
    Filed: September 30, 1997
    Date of Patent: March 16, 1999
    Assignee: MEMC Electronic Materials, Inc.
    Inventor: Robert H. Fuerhoff
  • Patent number: 5882417
    Abstract: A platen supports a wafer during the deposition of tungsten, metal nitrides, other metals, and silicides in a chemicalvapor deposition reactor. A deposition control gas that includes a suitable inert gas such as argon or a mixture of inert and reactant gases such as argon and hydrogen is introduced through a restrictive opening into an ambient in the reactor. An exclusion guard aligned with the platen has an extension extending over a frontside peripheral region of the wafer. Deposition control gas is introduced under the exclusion guard extension and exits through a restrictive opening between the exclusion guard extension and a wafer frontside peripheral region. The restrictive opening provides a uniform pressure of deposition control gas at the edge and frontside of the wafer to prevent deposition on the wafer edge and backside.
    Type: Grant
    Filed: December 31, 1996
    Date of Patent: March 16, 1999
    Assignee: Novellus Systems, Inc.
    Inventors: Everhardus P. van de Ven, Eliot K. Broadbent, Jeffrey C. Benzing, Barry L. Chin, Christopher W. Burkhart, Lawrence C. Lane, Edward John McInerney
  • Patent number: 5882399
    Abstract: The aluminum <111> crystal orientation content of an aluminum interconnect layer or the copper <111> crystal orientation content of a copper interconnect can be maintained at a consistently high value during the processing of an entire series of semiconductor substrates in a given process chamber. To provide the stable and consistent aluminum <111> content, or the stable and consistent copper <111> content, it is necessary that the barrier layer structure underlying the aluminum or the copper have a consistent crystal orientation throughout the processing of the entire series of substrates, as well. We have determined that to ensure the consistent crystal orientation content of the barrier layer structure, it is necessary to form the first layer of the barrier layer structure to have a minimal thickness of at least about 150 .ANG., to compensate for irregularities in the crystal orientation which may by present during the initial deposition of this layer.
    Type: Grant
    Filed: August 23, 1997
    Date of Patent: March 16, 1999
    Assignee: Applied Materials, Inc.
    Inventors: Kenny King-tai Ngan, Barry Hogan, Seshadri Ramaswami