Patents Examined by R. Paladugu
  • Patent number: 5230712
    Abstract: A method for making an electrochemical capacitor is disclosed. A plurality of bipolar electrodes having porous conductive oxide coatings on opposite sides of a thin metal foil are first produced in a fixture assembly using sol-gel processing techniques. A dielectric oxide coating is then applied to one or both conductive coatings using the sol-gel process. A stack of a plurality of the bipolar electrodes with adjacent electrodes separated by a predetermined amount of a solid electrolyte is assembled. The stacked assembly is heated to a temperature above the electrolyte melting point allowing the molten electrolyte to infiltrate the porous coatings. Pressure is applied to the stacked assembly sufficient to produce intimate contact between adjacent surfaces of the bipolar electrodes while expelling excess liquid from between the electrode surfaces. The stacked assembly is cooled in a controlled fashion to produce a laminate structure.
    Type: Grant
    Filed: September 28, 1992
    Date of Patent: July 27, 1993
    Inventor: M. Dean Matthews
  • Patent number: 5229320
    Abstract: Disclosed is a method which enabled the precise formation of a group of quantum dots. A device which functions on the principle of a transmission type electron microscope is used to produce a beam of electrons which are passed through a thin crystal membrane in order to produce an electron beam diffraction image. The energy distribution of the diffracted electron beam is used to produce masks, enable epitaxial growth and dry etching involved with the microscopic fabrication operations. For example, a thin GaAs membrane is used to form a diffracted electron beam image on a GaAs layer formed on a substrate. Carbon is then supplied and used to form carbon layers on the the locations where the beam energy is strongest. These carbon layers are used as a mask which allow selective etching of the GaAs layer.
    Type: Grant
    Filed: July 28, 1992
    Date of Patent: July 20, 1993
    Assignee: Sony Corporation
    Inventor: Ryuichi Ugajin
  • Patent number: 5225375
    Abstract: For plasma enhanced chemical vapor processing of semiconductor substrates, substrates are mounted on an elongate support, in a spaced parallel array. A shaft is rotatably mounted on the support and has electrode holding means, the electrodes alternating in polarity. The shaft, when rotated, moves the electrodes down in between the substrates, for positioning of the assembly in a reaction chamber for processing. After processing, and removal from the chamber, the shaft is rotated to move the electrodes out from between the substrates, to permit easy loading and unloading. The substrates are normally supported on boats positioned on the support. A particularly effective rf power feedthrough connects rf power from a power source through the door of the chamber.
    Type: Grant
    Filed: May 20, 1991
    Date of Patent: July 6, 1993
    Assignee: Process Technology (1988) Limited
    Inventors: Kamel Aite, R. B. DesBrisay, Lee Danisch
  • Patent number: 5223002
    Abstract: Highly conducting polyaniline is produced in situ in a tantalum capacitor by subjecting an excess of monomeric aniline to a solution having a low concentration of ammonium persulfate reagent. The monomer is oxidized by the reagent in preference to the polymer, so that the presence of excess monomer protects the polymer as it is produced against further oxidation to a less conductive species.
    Type: Grant
    Filed: October 31, 1991
    Date of Patent: June 29, 1993
    Assignee: Sprague Electric Company
    Inventor: Sidney D. Ross
  • Patent number: 5219786
    Abstract: A semiconductor layer annealing method comprises a step of heating a wafer consisting of a substrate and a semiconductor layer formed thereon by a heating means at a preheating temperature which will not exercise adverse thermal effect on the substrate, heating a portion of a small area of the semiconductor layer by a pulse of an excimer laser beam in one annealing cycle to a temperature higher than the preheating temperature and high enough to anneal the portion of the semiconductor layer, and repeating the annealing cycle to anneal the successive portions of the semiconductor layer sequentially.
    Type: Grant
    Filed: June 11, 1992
    Date of Patent: June 15, 1993
    Assignee: Sony Corporation
    Inventor: Takashi Noguchi
  • Patent number: 5213985
    Abstract: A relatively simple optical monitoring technique is utilized to measure temperature within a processing chamber. A III-V direct-bandgap semiconductor is optically excited to emit photoluminescence (PL). Spectral resolution of the emitted PL provides a direct measure of the bandgap of the semiconductor. In turn, the temperature of the semiconductor is derived from the bandgap measurement.
    Type: Grant
    Filed: May 22, 1991
    Date of Patent: May 25, 1993
    Assignee: Bell Communications Research, Inc.
    Inventors: Claude J. Sandroff, Francoise S. Sandroff
  • Patent number: 5210052
    Abstract: A method for fabricating a heteroepitaxial semiconductor substrate body used as a substrate of a compound semiconductor device. The heteroepitaxial semiconductor substrate body comprises a semiconductor substrate of a first semiconductor material and an epitaxial layer of a second semiconductor material grown heteroepitaxially on the semiconductor substrate. The method comprises steps of growing the epitaxial layer on the semiconductor substrate heteroepitaxially to form the heteroepitaxial semiconductor substrate body, depositing a stress inducing layer on a top surface of the epitaxial layer so as to induce a stress in the epitaxial layer, applying a cyclic annealing process for repeatedly and alternately holding the heteroepitaxial substrate body including the stress inducing layer deposited on the epitaxial layer at a first temperature and at a second temperature lower than the first temperature, and removing the stress inducing layer from the top surface of the epitaxial layer.
    Type: Grant
    Filed: May 13, 1992
    Date of Patent: May 11, 1993
    Assignee: Fujitsu Limited
    Inventor: Kanetake Takasaki
  • Patent number: 5208167
    Abstract: A method for producing a SOI substrate comprising: a step of forming a first opening to an insulating film on a semiconductor substrate and then forming semiconductor crystal layer by epitaxial growth over the first opening and the insulating film; a step of forming a second opening by partially removing the semiconductor crystal layer; a step of forming an integrated insulating film, and a step of forming an integrated semiconductor crystal layer. With the present invention, a semiconductor crystal layer can be formed on an insulating film on a substrate with large area, wherein the crystal layer and the substrate is completely insulated from each other. Further even from such materials as hard to form monocrystal substrate, a substrate can be easily obtained.
    Type: Grant
    Filed: June 19, 1992
    Date of Patent: May 4, 1993
    Assignee: Rohm Co., Ltd.
    Inventor: Tomofumi Nakamura
  • Patent number: 5208187
    Abstract: A metal film forming method comprises steps of:forming a non-monocrystalline metal film principally composed of aluminum, in contact, at least in a part thereof, with a monocrystalline metal principally composed of aluminum; andheating the non-monocrystalline metal film to convert at least a part thereof into monocrystalline state.
    Type: Grant
    Filed: July 8, 1991
    Date of Patent: May 4, 1993
    Inventors: Kazuo Tsubouchi, Kazuya Masu
  • Patent number: 5190893
    Abstract: A local interconnect structure is formed in a semiconductor device. In one form, the semiconductor device has two conductive features (one of 54) and (56) which are to be electrically connected. A layer of metal (62), for instance titanium, is deposited on the device. The layer of metal is patterned to form a strap (64) which connects the two conductive features. After patterning the layer of metal to form the strap, the strap is thermally nitrided to form a conductive metal nitride local interconnect (66).
    Type: Grant
    Filed: April 1, 1991
    Date of Patent: March 2, 1993
    Assignee: Motorola Inc.
    Inventors: Robert E. Jones, Jr., Hisao Kawasaki
  • Patent number: 5189770
    Abstract: Solid electrolyte capacitors are produced in such a way that a formed metallic anode body which has pores passing through it is arranged on a working electrode, and a conductive polymer is deposited in the pores of the anode body by electochemical polymerization of a monomer in the liquid phase, in the presence of a conducting salt. The polymer is provided with a contact point.
    Type: Grant
    Filed: August 8, 1991
    Date of Patent: March 2, 1993
    Assignee: Siemens Aktiengesellschaft
    Inventors: Manfred Waidhas, Kurt Pantel, Gerhard Richter
  • Patent number: 5187116
    Abstract: A process for preparing an electroluminescent device of a compound semiconductor comprising a step (A) of epitaxially forming over a semiconductor substrate an electroconductive layer of a compound semiconductor and an electroluminescent layer of a p-n junction type compound semiconductor placed over the electroconductive layer and a step (B) of forming a pair of ohmic electrodes as electrically connected to each of said layers, both of the steps (A) and (B) being performed by using molecular beam growth under the irradiation with a light beam.
    Type: Grant
    Filed: July 3, 1990
    Date of Patent: February 16, 1993
    Assignee: Sharp Kabushiki Kaisha
    Inventors: Masahiko Kitagawa, Yoshitaka Tomomura, Kenji Nakanishi