Abstract: An integrated circuit device is disclosed. In one embodiment, the device has a semiconductor chip having an electrical circuit that is connected to a bonding pad. A metal layer overlies the bonding pad, and a metal bump is connected to the metal layer. The metal bump receives power for the electrical circuit. The method of manufacture allows a designer to form a power supply bus in the metal layer. The metal layer may lie over an active circuit of the semiconductor chip.

Abstract: A semiconductor device includes an insulating film having an opening and first and second surfaces, a semiconductor chip positioned inside the opening and having first and second surfaces and a plurality of electrodes formed on its first surface, a plurality of leads supported on the first surface of the insulation film and connected to the electrodes of the semiconductor chip, first and second protective films facing the first and second surfaces of the insulating film, respectively, and a bonding agent disposed between the first and second protective films sealing the semiconductor chip and bonding the films together.

Abstract: The emitter region of a speed-up transistor is created in a base of a final transistor of a Darlington device and has a relatively low dopant concentration and small thickness.

Abstract: In an arrangement for packaging planar arrays of circuit components including a plurality of essentially parallel layers in which the layers lie closely adjacent one another, one or more of the layers including a substrate of insulating material having circuit board apparatus imbedded therein, the improvement including apparatus positioned against at least one of the layers for removing heat from the arrangement.

Abstract: A semiconductor device includes a plurality of lead frames on which at least one semiconductor pellet is formed, a dummy pellet on at least one of the plurality of lead frames, wires for connecting electrodes of the semiconductor pellets with electrodes of the dummy pellet.

Abstract: A flexible circuit film is used in a surface mountable pre-formed chip carrier cavity package as a direct interconnect between the integrated circuit chip and external bonding pads on a printed circuit board. The IC chip carrier of the present invention is comprised of a square or rectangular base having a central cavity; an IC chip mounted in the cavity and held therein by an adhesive; a lid having a complementary shape to the upper surface of the base; and a flexible circuit sheet sandwiched between the base and lid. The flexible circuit conforms to the top surface of the base due to various cuts or cutouts therein depending upon the specific package construction. Etched copper circuitry on the flex circuit forms interconnects between I/O pads on the IC chip and the outer periphery of the package. The package enables the use of more than 80 and up to more than 300 I/O leads per chip. The base, circuit film, and lid are bonded together with a suitable adhesive.

Abstract: A wiring substrate, a film carrier, a semiconductor device made by using the film carrier, and a mounting structure comprising the semiconductor device are disclosed.The wiring substrate comprises:a conductor pattern which has a bonding pad and is formed on the rear surface of an insulating support;at least one of minute through-holes which are provided in a region of the insulating support where the bonding pad is in contact therewith, or which are provided a region of the insulating support where the bonding pad is in contact therewith and in the vicinity of the region, the through-holes running in the direction of the thickness of the insulating support;a conductive passage which is made of a metal material and which is formed in the through-holes that are provided in a region of the insulating support where the bonding pad is in contact therewith; anda bump-like metal protrusion which is formed on the conductive passage and which is protruded from the front surface of the insulating support.

Abstract: A contact opening through an insulating layer is filled with metal and etched back to form a metal plug within the opening. A metal interconnect line can then be formed over the contact, and makes electrical contact with the metal plug. Since the contact opening is filled by the metal plug, it is not necessary for the metal signal line to have a widened portion in order to ensure enclosure.

Abstract: A working point adjusting circuit for a power amplifier. When this simple circuit is connected into a Class B transistor power amplifier it adjusts the working point of the transistors in the output circuit of the power amplifier to the linear portion of the current-voltage characteristics of the transistor so the amplifier works in the level of a Class A amplifier. It provides many significant advantages including (1) much higher energy efficiency on output transistors; (2) much less signal distortion on loaded speakers; (3) simple circuitry for increased reliability; and (4) low component count for reduced costs.

Abstract: A cascode transistor configuration includes an input terminal for receiving the input signal, an output terminal for outputting the output signal and bass and emitter terminals connectable to ground. Each of a predetermined plurality of common-base heterojunction bipolar transistors (HBTs) has a base coupled to the base terminal, and a collector coupled to the support output terminal. Each of the predetermined plurality of common-emitter HBTs is associated with one of the common-base HBTs. Each common-emitter HBT also has a base coupled to the input terminal, an emitter coupled to the emitter terminal, and a collector coupled to only the emitter of the associated common-base HBT.

Abstract: A preferred embodiment of the invention is a poly input resistor located underneath, rather than alongside, an IC wirebond pad. This offers the advantages of a more efficient layout, more contacts connecting the pad to the resistor, a better contact configuration, and a larger, higher current resistor.

Abstract: In electronic ballast having inverter rectifiers for fluorescent lamps, a regulation of the lamp current or of the lamp power is usually used in order to stabilize the lighting current independently of tolerances of the electrical properties of the fluorescent lamp or their aging phenomena. When such a regulation is simultaneously utilized for dimming the fluorescent lamp, difficulties arise at the lower limit of the dimming range at, for example, 1% of the nominal light power. The range of brightness at the lower limit is regulated on the basis of an additional regulation, dependent on the discharge resistance of the fluorescent lamp. An auxiliary measured quantity resulting therefrom is superimposed on the actuating quantity of the regulator that results from a reference/actual value comparison of the current or power regulation for the purpose of stabilizing the lamp current.

Abstract: An arrangement for interconnecting high density signals of integrated circuits provides minimal cross-talk, low noise and controlled impedance. A thermally conductive baseplate is used to support integrated circuit die in a multi-layered substrate. The integrated circuit die are thermally coupled to the baseplate, and the multi-layered substrate includes apertures therethrough for receiving the integrated circuit die. Tape automated bonding is used to connect leads on the integrated circuit die with conductors disposed on layers in the substrate. Other aspects of the arrangement include providing a power flex-connector and a signal flex-connector to connect the multi-layered substrate to an external power source and to a printed circuit board, respectively. To further minimize noise interference, the multi-layered substrate includes separate power and ground layers which are adjacent to one another.

Abstract: The present invention relates to a semiconductor casing which permits transmitting ultraviolet rays to a semiconductor chip within the casing. The semiconductor casing includes the substrate formed by a thin metal plate for mounting the semiconductor chip, a ceramic frame fixed to the periphery of the substrate, a ceramic cap which covers the semiconductor chip, is mounted on the ceramic frame and allows transmission of ultraviolet rays, and leads which are sandwiched between the ceramic frame and the ceramic cap to allow the electrical connection of the semiconductor chip.

Abstract: There is disclosed a method for making a light-emitting diode array capable of realizing large output and large-scale integration by using a heterogenous film which can electrically insulate between LEDs, (LEDs) by the diffusion of an impurity into a substrate. The improved LED array manufacturing method includes the steps of: forming a luminescent layer, of a first conductivity type, a transparent layer and a cap-layer over the semiconductor substrate; forming of a cap layer made into a given pattern by etching a given portion of said cap layer; forming of a diffusion region converted into the first conductivity type by the injection of an impurity into a given portion of the transparent layer; forming an oxide film on the entire surface except the area where the cap layer is covering the transparent layer; and forming an electrode over the cap layer and a common electrode under the semiconductor substrate.

Abstract: A silicon carbide light emitting diode having a pn junction is disclosed which comprises a semiconductor substrate, a first silicon carbide single-crystal layer of one conductivity formed on the substrate, and a second silicon carbide single-crystal layer of the opposite conductivity formed on the first silicon carbide layer, the first and second silicon carbide layers constituting the pn junction, wherein at least one of the first and second silicon carbide layers contains a tetravalent transition element as a luminescent center.

Abstract: A multichip electronic package uses a silicon substrate for chip mounting and interconnects, micro-machined inverted and non-inverted truncated vias for intrinsically hermetically sealed I/O connections, and an anodically bonded silicon cover, with support posts. Stacked, colocated and inverted vias are provided for increased chip and interconnect density within an intrinsically sealed, thermally matched package.

Abstract: With the reduction in the size of semiconductor integrated circuit devices, there have been increases in the resistance at the contact portions of metal interconnections and in the incidence of contact failure. To solve these problems, the present invention provides a novel interconnection structure.

Abstract: A lead frame for orienting and then mounting a plurality of clip leads on a semi-conductor device or substrate and method.

Abstract: A method for manufacturing a lead frame comprises the steps of covering, with a cover film, a die to which an electronic device is attached and a conducting section of a lead section to be electrically connected to the die, covering the whole of the die and lead section and the cover film with an inorganic protective film, and removing the cover film and the protective film formed over the cover film to partly expose the die and the conducting section for electric connection.