Patents Examined by Raj Gupta
  • Patent number: 8017939
    Abstract: The present disclosure relates to an organic memory device and a fabrication method thereof. The organic memory device comprises a first electrode, a second electrode, and an organic memory layer situated between the electrodes, wherein a metallic nanoparticle layer is further situated between the first electrode and the organic memory layer. Since the organic memory device may be operated using only positive voltages, a 1D1R device composed of one diode and one resistor can be realized and a passive matrix can be realized due to the 1D1R structure. Accordingly, the organic memory device enables higher integration, ultrahigh speeds, larger capacities, lower power consumption, and/or lower prices.
    Type: Grant
    Filed: April 24, 2007
    Date of Patent: September 13, 2011
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Won Jae Joo, Seong Jae Choi, Jae Young Choi, Sang Kyun Lee, Kwang Hee Lee
  • Patent number: 8008647
    Abstract: There is provided a nitride semiconductor device including an active layer of a superlattice structure. The nitride semiconductor device including: a p-type nitride semiconductor layer; an n-type nitride semiconductor layer; and an active layer disposed between the p-type and n-type nitride layers, the active layer comprising a plurality of quantum barrier layers and quantum well layers deposited alternately on each other, wherein the active layer has a superlattice structure where the quantum barrier layer has a thickness for enabling a carrier injected from the p-type and n-type nitride semiconductor layers to be tunneled therethrough, and at least one of the quantum barrier layers has an energy band gap greater than another quantum barrier layer adjacent to the n-type nitride semiconductor layer.
    Type: Grant
    Filed: October 10, 2007
    Date of Patent: August 30, 2011
    Assignee: Samsung LED Co., Ltd.
    Inventors: Seong Eun Park, Min Ho Kim, Jae Woong Han
  • Patent number: 7994520
    Abstract: Disclosed are a semiconductor light emitting device comprising a single crystalline buffer layer and a manufacturing method thereof. The semiconductor light emitting device comprises a single crystalline buffer layer, and a compound semiconductor structure comprising III and V group elements on the single crystalline buffer layer.
    Type: Grant
    Filed: November 24, 2008
    Date of Patent: August 9, 2011
    Assignee: LG Innotek Co., Ltd.
    Inventor: Kyong Jun Kim
  • Patent number: 7985695
    Abstract: An oxide film formation method comprises steps of: generating a plasma from a gas mixture containing an inert gas and an oxidizing gas whose mixing ratio to the inert gas is higher than 0, and is 0.007 or lower; and forming an oxide film on a surface of a silicon substrate by using the plasma.
    Type: Grant
    Filed: September 25, 2008
    Date of Patent: July 26, 2011
    Assignee: Canon Kabushiki Kaisha
    Inventor: Nobuyuki Endo
  • Patent number: 7982216
    Abstract: A TFT is provided which includes, on a substrate, at least a gate electrode, a gate insulating layer, an active layer containing an amorphous oxide semiconductor, a source electrode, and a drain electrode, wherein a carrier concentration of the active layer is 3×1017 cm?3 or more and a film thickness of the active layer is 0.5 nm or more and less than 10 nm. A TFT is provided which has a low OFF current and a high ON-OFF ratio, and is improved in environmental temperature dependency. Also, a display using the TFT is provided.
    Type: Grant
    Filed: November 12, 2008
    Date of Patent: July 19, 2011
    Assignee: Fujifilm Corporation
    Inventor: Shinji Imai
  • Patent number: 7973336
    Abstract: Growth of multilayer films is carried out in a manner which allows close control of the strain in the grown layers and complete release of the grown films to allow mounting of the released multilayer structures on selected substrates. A layer of material, such as silicon-germanium, is grown onto a template layer, such as silicon, of a substrate having a sacrificial layer on which the template layer is formed. The grown layer has a lattice mismatch with the template layer so that it is strained as deposited. A top layer of crystalline material, such as silicon, is grown on the alloy layer to form a multilayer structure with the grown layer and the template layer. The sacrificial layer is preferentially etched away to release the multilayer structure from the sacrificial layer, relaxing the grown layer and straining the crystalline layers interfaced with it.
    Type: Grant
    Filed: May 8, 2007
    Date of Patent: July 5, 2011
    Assignee: Wisconsin Alumni Research Foundation
    Inventors: Donald E. Savage, Michelle M. Roberts, Max G. Lagally
  • Patent number: 7973316
    Abstract: An object is to provide a semiconductor device which is not easily broken even if stressed externally and a method for manufacturing such a semiconductor device. A semiconductor device includes an element layer including a transistor in which a channel is formed in a semiconductor layer and insulating layers which are formed as an upper layer and a lower layer of the transistor respectively, and a plurality of projecting members provided at intervals of from 2 to 200 ?m on a surface of the element layer. The longitudinal elastic modulus of the material for forming the plurality of projecting members is lower than that of the materials of the insulating layers.
    Type: Grant
    Filed: March 19, 2008
    Date of Patent: July 5, 2011
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventor: Hideto Ohnuma
  • Patent number: 7968924
    Abstract: In a semiconductor device comprising a capacitive element, an area of the capacitive element is reduced without impairing performance, and further, without addition of an extra step in a manufacturing process.
    Type: Grant
    Filed: September 29, 2008
    Date of Patent: June 28, 2011
    Assignee: Renesas Electronics Corporation
    Inventor: Akihiko Sato
  • Patent number: 7964948
    Abstract: A chip stack may include a first chip and a second chip stacked on the first chip. Each of the first and second chips may include a substrate having an active surface and an inactive surface opposite to the active surface; an internal circuit in the active surface; an I/O chip pad on the active surface and connected to the internal circuit through an I/O buffer; and a I/O connection pad connected to the I/O chip pad through the I/O buffer by a circuit wiring. A redistributed I/O chip pad layer may be on the active surface of the first chip, the redistributed I/O chip pad layer redistributing the I/O chip pad. The I/O connection pads of the first chip and the second chip may be electrically connected to each other by an electrical connecting part.
    Type: Grant
    Filed: April 25, 2007
    Date of Patent: June 21, 2011
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Jong-joo Lee, Sun-won Kang
  • Patent number: 7939943
    Abstract: A nitride semiconductor device with a p electrode having no resistance between itself and other electrodes, and a method of manufacturing the same are provided. A p electrode is formed of a first Pd film, a Ta film, and a second Pd film, which is an antioxidant film for preventing oxidation of the Ta film, and on a p-type contact layer of a nitride semiconductor. On the second Pd film, a pad electrode is formed. The second Pd film as an antioxidant film is formed on the entire upper surface of the Ta film which forms the p electrode, to prevent oxidation of the Ta film. This inhibits the resistance between the p electrode and the pad electrode, thereby preventing a failure in contact between the p electrode and the pad electrode and providing the low-resistance p electrode.
    Type: Grant
    Filed: November 11, 2008
    Date of Patent: May 10, 2011
    Assignee: Mitsubishi Electric Corporation
    Inventors: Katsuomi Shiozawa, Kyozo Kanamoto, Toshiyuki Oishi, Hiroshi Kurokawa, Kenichi Ohtsuka, Yoichiro Tarui, Yasunori Tokuda
  • Patent number: 7939380
    Abstract: A method for manufacturing a semiconductor component that includes a leadframe having a non-metallic base structure and an intermediate leadframe structure. The non-metallic base structure may be, among other things, paper, cellulose, or plastic. A layer of electrically conductive material is formed over the non-metallic base structure. A circuit element attach structure and a plurality of leadframe leads are formed from the layer of electrically conductive material. A circuit element is coupled to the circuit element attach structure and electrically coupled to the plurality of leadframe leads. The circuit element is encapsulated and at least the non-metallic base structure is removed. Alternatively, a plurality of leadframe leads may be formed on the electrically conductive layer and a circuit element is placed over the electrically conductive layer. The circuit element is electrically coupled to the plurality of leadframe leads and encapsulated.
    Type: Grant
    Filed: March 17, 2008
    Date of Patent: May 10, 2011
    Assignee: Semiconductor Components Industries, LLC
    Inventors: Shutesh Krishnan, Soon Wei Wang, Jatinder Kumar
  • Patent number: 7929321
    Abstract: A DC-to-DC converter includes a high-side transistor and a low-side transistor wherein the high-side transistor is implemented with a high-side enhancement mode MOSFET. The low side-transistor further includes a low-side enhancement MOSFET shunted with a depletion mode transistor having a gate shorted to a source of the low-side enhancement mode MOSFET. A current transmitting in the DC-to-DC converter within a time-period between T2 and T3 passes through a channel region of the depletion mode MOSFET instead of a built-in diode D2 of the low-side MOSFET transistor. The depletion mode MOSFET further includes trench gates surrounded by body regions with channel regions immediately adjacent to vertical sidewalls of the trench gates wherein the channel regions formed as depletion mode channel regions by dopant ions having electrical conductivity type opposite from a conductivity type of the body regions.
    Type: Grant
    Filed: August 22, 2008
    Date of Patent: April 19, 2011
    Assignee: Force-Mos Technology Corp
    Inventor: Fwu-Iuan Hshieh
  • Patent number: 7928532
    Abstract: A fuse box includes a fuse pattern having a rugged profile and an interlayer insulating film including a fuse blowing window to fill the fuse pattern.
    Type: Grant
    Filed: December 28, 2007
    Date of Patent: April 19, 2011
    Assignee: Hynix Semiconductor Inc.
    Inventor: Seung Pyo Park
  • Patent number: 7923721
    Abstract: An organic thin film transistor including: a substrate; a gate electrode placed on the substrate; a gate insulating film placed on the gate electrode; a source electrode and a drain electrode which are placed on the gate insulating film; an organic semiconductor layer placed on the gate insulating film between the source electrode and the drain electrode; a hole transport layer placed on the organic semiconductor layer; an electron transport layer placed on the hole transport layer; and a conductor layer placed on the electron transport layer; the organic thin film transistor which characteristics are stable by being protected from oxygen or moisture and being protected electromagnetically and which is suitable for integration.
    Type: Grant
    Filed: August 19, 2008
    Date of Patent: April 12, 2011
    Assignee: Rohm Co., Ltd.
    Inventors: Suguru Okuyama, Yoshiaki Oku, Noriyuki Shimoji
  • Patent number: 7923719
    Abstract: In the present invention, a semiconductor device that has a nonvolatile memory element to which data can be written at times other than during manufacture and in which forgery and the like performed by rewriting of data can be prevented is provided. In addition, a semiconductor device in which a high level of integration is possible is provided. Furthermore, a semiconductor device in which miniaturization is possible is provided. In a semiconductor device having a memory element that includes a first conductive layer, a second conductive layer, and an organic compound layer interposed between the first conductive layer and the second conductive layer; the second conductive layer is connected to a wiring, formed in the same way as the first conductive layer is formed, through an opening formed in the organic compound layer.
    Type: Grant
    Filed: April 25, 2007
    Date of Patent: April 12, 2011
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Shunpei Yamazaki, Kiyoshi Kato, Ryoji Nomura
  • Patent number: 7923811
    Abstract: An electronic fuse (“E-fuse”) cell is formed on a semiconductor substrate. The E-fuse cell has a fuse element with a fuse link extending from a first fuse terminal across a thick dielectric structure to a second fuse terminal. The first and second fuse terminals are separated from the semiconductor substrate by a thin dielectric layer.
    Type: Grant
    Filed: March 6, 2008
    Date of Patent: April 12, 2011
    Assignee: Xilinx, Inc.
    Inventors: Hsung Jai Im, Sunhom Paak, Boon Yong Ang
  • Patent number: 7919803
    Abstract: A semiconductor memory device in which a plurality of capacitors each including a columnar lower electrode, a capacitor insulation film and an upper electrode are stacked with interlayer films therebetween, a contact plug connects an upper face of each lower electrode of a lower layer with a bottom face of each lower electrode of an upper layer, and another contact plug connects upper electrodes of the capacitors in respective layers with each other.
    Type: Grant
    Filed: September 19, 2008
    Date of Patent: April 5, 2011
    Assignee: Elpida Memory, Inc.
    Inventor: Naoki Yokoi
  • Patent number: 7915995
    Abstract: A resistive circuit includes a first terminal and a second terminal and polycrystalline first and second resistive segments coupled between the first and second terminals. A third terminal A is coupled to the first resistive segment, and a third terminal B is coupled to the second resistive segment. The third terminal A has a first voltage with respect to the first terminal, and the third terminal B has a second voltage with respect to the second terminal. With this arrangement, the non-linearity of resistance of the first resistive segment at least partially compensates for non-linearity of resistance of the second resistive segment.
    Type: Grant
    Filed: September 29, 2009
    Date of Patent: March 29, 2011
    Assignee: Cirrus Logic, Inc.
    Inventors: Hua Yang, Ammisetti Prasad, John L. Melanson
  • Patent number: 7902668
    Abstract: A semiconductor chip constitutes a semiconductor device in which a plurality of semiconductor chips are laminated. The semiconductor chip includes a plurality of terminals which are to be connected to another semiconductor chip. At least one terminal of the terminals has a higher height than that of another terminal.
    Type: Grant
    Filed: March 20, 2008
    Date of Patent: March 8, 2011
    Assignee: Kabushiki Kaisha Toshiba
    Inventor: Koichi Sato
  • Patent number: 7888181
    Abstract: A semiconductor device is made by providing a metal substrate for supporting the semiconductor device. Solder bumps are connected to the substrate. In one embodiment, a conductive material is deposited over the substrate and is reflowed to form the solder bumps. A semiconductor die is mounted to the substrate using a die attach adhesive. The semiconductor die has a plurality of contact pads formed over a surface of the semiconductor die. An encapsulant material is deposited over the solder bumps and the semiconductor die. The encapsulant is etched to expose the contact pads of the semiconductor die. A first redistribution layer (RDL) is formed over the encapsulant to connect each contact pad of the semiconductor die to one of the solder bumps. The substrate is removed to expose the die attach adhesive and a bottom surface of the solder bumps.
    Type: Grant
    Filed: September 22, 2008
    Date of Patent: February 15, 2011
    Assignee: STATS ChipPAC, Ltd.
    Inventors: Zigmund R. Camacho, Lionel Chien Hui Tay, Henry D. Bathan, Jeffrey D. Punzalan